Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 2, 1998, Pages 253-258

  Idei, Youji ^b,d   Shimohigashi, Katsuhiro ^{a,b,e,f,g,h,i}   Aoki, Masakazu ^a,b,d,j,k   Noda, Hiromasa ^a,b,d   Iwai, Hidetoshi ^b   Sato, Katsuyuki ^a,b   Tachibana, Tadashi ^c  

^a IEEE

^b HITACHI LTD   (Japan)

^c Texas Instruments Japan Ltd   (Japan)

^d UNIVERSITY OF TOKYO   (Japan)

^e KYUSHU UNIVERSITY   (Japan)

^f STANFORD UNIVERSITY   (United States)

^g Planning Office

^h ULSI Research Center

ⁱ Memory Business Operation ^*  (Japan)

^j UNIVERSITY OF MICHIGAN   (United States)

^k Institute of Electronics   (Japan)

more..

Author keywords

DRAM; Period; PROM; Refresh; Register

Indexed keywords

DESIGN; PROM; SEMICONDUCTOR STORAGE; TECHNOLOGY;

LOW-POWER DRAM; REGISTER;

DATA STORAGE EQUIPMENT;

EID: 0032001924     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.658627     Document Type: Article

References (9)

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