A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 1, 2005, Pages 186-193

  Yamaoka, Masanao ^a   Shinozaki, Yoshihiro ^a   Maeda, Noriaki ^b   Shimazaki, Yasuhisa ^b   Kato, Kei ^b   Shimada, Shigeru ^b   Yanagisawa, Kazumasa ^b   Osada, Kenichi ^a  

^a HITACHI LTD   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

Application processor; Cellular phone; Low leakage; Low power; SRAM

Indexed keywords

CELLULAR TELEPHONE SYSTEMS; ELECTRIC POWER UTILIZATION; ELECTRONIC STRUCTURE; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; MOSFET DEVICES; THERMAL EFFECTS;

APPLICATION PROCESSORS; CELLULAR PHONES; LOW LEAKAGE; LOW POWER;

STATIC RANDOM ACCESS STORAGE;

EID: 11944250195     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.838014     Document Type: Conference Paper

References (5)

1. T. Kamei et al., "A resume-standby application processor for 3G cellular phones," IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, p. 336, 2004.
2. K. Osada et al., "Universal-Vdd 0.65-2.0 V 32 kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2001, pp. 168-169.
3. K. Osada et al., "16.7 fA/cell tunnel-leakage-suppressed 16 Mb SRAM for handling cosmic-ray-induced multierrors," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2003, pp. 302-303.
4. A. J. Bhavnagarwala et al., "A pico-joule class, 1 GHz, 32 KByte × 64 b DSP SRAM with self reverse bias," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2003, pp. 251-252.
5. K. Nii et al., "A 90 nm low power 32 KByte embedded SRAM with gate leakage suppression circuit for mobile applications," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2003, pp. 247-250.