A 1.35V 4.3GB/s 1gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 132-133

  Jeong, Bong Hwa ^a   Lee, Jongwon ^a   Lee, Yin Jae ^a   Kang, Tae Jin ^a   Lee, Joo Hyeon ^a   Hong, Duck Hwa ^a   Kim, Jae Hoon ^a   Lee, Eun Ryeong ^a   Kim, Min Chang ^a   Lee, Kyung Ha ^a   Park II, Sang ^a   Son, Jong Ho ^a   Lee, Sang Kwon ^a   Yoo, Seong Nyuh ^a   Kim, Sung Mook ^a   Kwon, Tae Woo ^a   Ahn, Jin Hong ^a   Kim, Yong Tak ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349283739     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977343     Document Type: Conference Paper

References (4)

1. T. Nagai, M. Wada, H. Iwai, et al., "A 65nm Low-Power Embedded DRAM with Extended Data-Retention Sleep Mode", ISSCC Dig. Tech. Papers, pp. 567-576, Feb. 2006.
2. K-H. Kyung, C-W. Kim, J-Y. Lee, et al., "A 800Mb/s/pin 2Gb DDR2 SDRAM using an 80nm Triple Metal Technology", ISSCC Dig. Tech. Papers, pp. 468-469, Feb. 2005.
3. S. Mutoh, T Douseki, Y. Matsuya, et al., "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS", IEEE J. Solid-State Circuits, pp. 847-854, Aug. 1995.
4. 2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme", ISSCC Dig. Tech. Papers, pp. 166-167, Feb. 1996.