Novel architecture to boost the vertical tunneling in tunnel field effect transistors

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2011, Pages

  Leonelli, D ^a,b   Vandooren, A ^a   Rooyackers, R ^a   Verhulst, A S ^a   Huyghebaert, C ^a   De Gendt, S ^a,b   Heyns, M M ^a,b   Groeseneken, G ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

DRIVE CURRENTS; LATERAL TUNNELING; NOVEL ARCHITECTURE; SOURCE REGION; SUBTHRESHOLD SWING; TUNNEL FIELD EFFECT TRANSISTOR; UNDOPED CHANNELS;

DIELECTRIC MATERIALS; ELECTRIC FIELDS; GATE DIELECTRICS; GATES (TRANSISTOR);

ARCHITECTURE;

EID: 83455169184     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOI.2011.6081704     Document Type: Conference Paper

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