A 1-V 5.2-GHz CMOS synthesizer for WLAN applications

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 11, 2004, Pages 1873-1882

  Leung, Gerry C T ^a   Luong, Howard C ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Clock generation; Integer N; Low power; Low voltage; Oscillator; Phase locked loop (PLL); Receiver; Synthesizer; Transceiver; VCO; WLAN

Indexed keywords

ELECTRIC POTENTIAL; FEEDBACK AMPLIFIERS; LOCAL AREA NETWORKS; MULTIPLYING CIRCUITS; OSCILLATORS (ELECTRONIC); RELIABILITY; TRANSCEIVERS; WIRELESS TELECOMMUNICATION SYSTEMS;

CLOCK GENERATION; INTEGER-N; LOW POWER; PHASE-LOCKED LOOP (PLL);

CMOS INTEGRATED CIRCUITS;

EID: 8344266107     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.835830     Document Type: Article

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