A 2.4-GHz dual-mode 0.18-μm CMOS transceiver for bluetooth and 802.11b

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 11, 2004, Pages 1916-1926

  Cho, Thomas Byunghak ^a   Kang, David ^a   Heng, Chun Huat ^b   Song, Bang Sup ^c  

^a Chrontel Inc   (United States)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Bluetooth; Complex filter; Dual mode; IEEE 802.11b; RF tranceivers; Wireless LAN

Indexed keywords

BLUETOOTH; COMPLEX FILTERS; DUAL MODES;

AMPLIFIERS (ELECTRONIC); COMPUTER ARCHITECTURE; COST EFFECTIVENESS; FUNCTIONS; LOCAL AREA NETWORKS; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; SPECTRUM ANALYSIS; SPURIOUS SIGNAL NOISE; WIRELESS TELECOMMUNICATION SYSTEMS;

CMOS INTEGRATED CIRCUITS;

EID: 8344232360     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.835835     Document Type: Article

References (24)

1. B. Razavi, "A 2.4-GHz CMOS receiver for IEEE 802.11 wireless LANs," IEEE J. Solid-State Circuits, vol. 34, pp. 1382-1385, Oct. 1999.
2. F. Op't Eynde et al., "A fully-integrated single-chip SOC for Bluetooth," in IEEE ISSCC Dig. Tech. Papers, Feb. 2001, pp. 196-197.
3. A. Ajjikuttira et al., "A fully-integrated CMOS RFIC for Bluetooth applications," in IEEE ISSCC Dig. Tech. Papers, Feb. 2001, pp. 198-199.
4. H. Darabi et al., "A 2.4 GHz CMOS transceiver for Bluetooth," in IEEE ISSCC Dig. Tech. Papers, Feb. 2001, pp. 200-201.
5. A. Zolfaghri, A. Chan, and B. Razavi, "A 2.4 GHz 34 mW CMOS transceiver for frequency-hopping and direct-sequence applications," in IEEE ISSCC Dig. Tech. Papers, 2001, pp. 418-419.
6. P. van Zeijl et al., "A Bluetooth radio in 0.18 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2002, pp. 86-87.
7. 2 silicon area," in IEEE ISSCC Dig. Tech. Papers, 2002, pp. 90-91.
8. C. Cojocaru et al., "A 43 mW Bluetooth transceiver with -91 dBm sensitivity," in IEEE ISSCC Dig. Tech. Papers, 2003, pp. 90-91.
9. H. Ishikuro et al., "A single-chip CMOS Bluetooth transceiver with 1.5 MHz IF and direct modulation transmitter," in IEEE ISSCC Dig. Tech. Papers, 2003, pp. 94-95.
10. C. Park et al., "A low power CMOS Bluetooth transceiver with a digital offset canceling DLL-based GFSK demodulator," in IEEE ISSCC Dig. Tech. Papers, 2003, pp. 96-97.
11. G. Chien, W. Feng, Y. Hsu, and L. Tse, "A 2.4 GHz CMOS transceiver and baseband processor chipset for 802.11b wireless LAN application," in IEEE ISSCC Dig. Tech. Papers, 2003, pp. 358-359.
12. W. Kluge, L. Dathe, R. Jaehne, S. Ehrenreich, and D. Eggert, "A 2.4 GHz CMOS transceiver for 802.11b wireless LANs," in IEEE ISSCC Dig. Tech. Papers, 2003, pp. 360-361.
13. H. Darabi et al., "A dual mode 802.11b/Bluetooth radio in 0.35 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2003, pp. 86-87.
14. T. Cho, D. Kang, S. Dow, C. Heng, and B. Song, "A 2.4 GHz dual-mode 0.18 μm CMOS transceiver for Bluetooth and 802.11b," in IEEE ISSCC Dig. Tech. Papers, 2003, pp. 88-89.
15. M. Perrott, T. Tewksbury, and C. Sodini, "A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation," IEEE J. Solid-State Circuits, vol. 32, pp. 2048-2060, Dec. 1997.
16. N. Filiol, T. Riley, C. Plett, and M. Copeland, "An agile ISM band frequency synthesizer with built-in GMSK data modulation," IEEE J. Solid-State Circuits, vol. 33, pp. 998-1008, July 1998.
17. S. Willingham, M. Perrott, B. Setterberg, A. Grzegorek, and B. McFarland, "An integrated 2.5 GHz ∑Δ frequency synthesizer with 5 μs settling and 2 Mb/s closed loop modulation," in IEEE ISSCC Dig. Tech. Papers, Feb. 2000, pp. 200-201.
18. T. Riley, M. Copeland, and T. Kwasniewski, "Delta-sigma modulation in fractional-N frequency synthesis," IEEE J. Solid-State Circuits, vol. 28, pp. 553-559, May 1993.
19. W. Rhee, B. Song, and A. Ali, "A 1.1 GHz CMOS fractional-N frequency synthesizer with a 3b third-order Δ∑ modulator," IEEE J. Solid-State Circuits, vol. 35, pp. 271-350, Oct. 2000.
20. C. Heng and B. Song, "A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO," IEEE J. Solid-State Circuits, vol. 38, pp. 848-854, June 2003.
21. A. Rofougaran, J. Rael, M. Rofougaran, and A. Abidi, "A 900 MHz CMOS LC-oscillator with quadrature outputs," in IEEE ISSCC Dig. Tech. Papers, Feb. 1996, pp. 316-317.
22. J. Crols and M. Steyaert, "Single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology," IEEE J. Solid-State Circuits, vol. 30, pp. 1483-1491, Dec. 1995.
23. _, "Low-IP topologies for high-performance analog front ends of fully integrated receivers," IEEE Trans. Circuits Syst. II, vol. 45, pp. 269-282, Mar. 1998.
24. B. Song, T. Cho, D. Kang, and S. Dow, "A 2 MHz GFSK I/Q receiver for Bluetooth with DC-tolerant bit slicer," in Proc. IEEE CICC, 2002, pp. 431-434.