FPGA-based high-performance and scalable block LU decomposition architecture

IEEE Transactions on Computers

Volumn 61, Issue 1, 2012, Pages 60-72

  Jaiswal, Manish Kumar ^a   Chandrachoodan, Nitin ^b  

^a ICFAI UNIVERSITY   (India)

^b INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

Author keywords

ATLAS; block LU; floating point arithmetics; FPGA; GPU; hardware acceleration; Intel MKL; LU decomposition; scaling; single double precision

Indexed keywords

ATLAS; FLOATING-POINT ARITHMETIC; GPU; HARDWARE ACCELERATION; INTEL-MKL; LU DECOMPOSITION; SCALING; SINGLE/DOUBLE PRECISION;

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); SCALE (DEPOSITS);

HARDWARE;

EID: 82555168407     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2011.24     Document Type: Article

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