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Volumn , Issue , 2011, Pages

A 220-225.9 GHz InP HBT single-chip PLL

Author keywords

dynamic frequency dividers; hetero junction bipolar transistors; Phase locked loops; voltage controlled oscillators

Indexed keywords

ACTIVE LOOP FILTERS; DYNAMIC FREQUENCY DIVIDER; INP-HBT; LOCKING RANGE; OUTPUT AMPLIFIERS; PHASE DETECTORS; SINGLE-CHIP; SUBHARMONICS; VOLTAGE CONTROLLED OSCILLATOR;

EID: 81455132296     PISSN: 15508781     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CSICS.2011.6062495     Document Type: Conference Paper
Times cited : (5)

References (8)
  • 2
    • 34547533765 scopus 로고    scopus 로고
    • A 50-GHz phase-locked loop in 0.13-&μυ;m CMOS
    • Aug.
    • C. Cao, Y. Ding, and K. K. O, "A 50-GHz phase-locked loop in 0.13-&μυ;m CMOS," IEEE J. Solid-State Circuits, vol. 42, pp. 1649-1656, Aug. 2007.
    • (2007) IEEE J. Solid-State Circuits , vol.42 , pp. 1649-1656
    • Cao, C.1    Ding, Y.2    O, K.K.3
  • 3
    • 70349389669 scopus 로고    scopus 로고
    • A 43.7 mW 96 GHz PLL in 65nm CMOS
    • Feb.
    • K.-H. Tsai, and S.-I. Liu, "A 43.7 mW 96 GHz PLL in 65nm CMOS,"ISSCC Dig. Tech. Papers, pp. 276-277, Feb. 2009.
    • (2009) ISSCC Dig. Tech. Papers , pp. 276-277
    • Tsai, K.-H.1    Liu, S.-I.2
  • 4
    • 34248641316 scopus 로고    scopus 로고
    • PLL architecture for 77-GHz FMCW radar systems with highly-linear ultra-wideband frequency sweeps
    • DOI 10.1109/MWSYM.2006.249555, 4014915, 2006 IEEE MTT-S International Microwave Symposium Digest
    • C. Wagner, A. Stelzer, and H. Jager, "PLL architecture for 77-GHz FMCW radar systems with highly-linear ultra-wideband frequency sweeps," IEEE MTT-S Int. Microwave Symp. Dig., pp. 399-402, Jun. 2006. (Pubitemid 46924235)
    • (2006) IEEE MTT-S International Microwave Symposium Digest , pp. 399-402
    • Wagner, C.1    Stelzer, A.2    Jager, H.3
  • 5
    • 44649199222 scopus 로고    scopus 로고
    • A 75-GHz phase-locked loop in 90-nm CMOS technology
    • Jun.
    • J. Lee, M. Liu, and H. Wang, "A 75-GHz phase-locked loop in 90-nm CMOS technology," IEEE J. Solid-State Circuits, pp. 1414-1426, Jun. 2008.
    • (2008) IEEE J. Solid-State Circuits , pp. 1414-1426
    • Lee, J.1    Liu, M.2    Wang, H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.