Copper pillar bump technology progress overview

ICEPT-HDP 2011 Proceedings - 2011 International Conference on Electronic Packaging Technology and High Density Packaging

Volumn , Issue , 2011, Pages 1133-1137

  Koh, Wei ^a   Lin, Barry ^a   Tai, Johnson ^a  

^a Powertech Technology Inc   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER BUMPS; COPPER PILLARS; EXPERIMENTAL STUDIES; FLIP CHIP; FLIP CHIP ASSEMBLIES; FLIP-CHIP PACKAGES; FORM FACTORS; IC PACKAGE; LOWER-POWER CONSUMPTION; METAL POSTS; MICRO-BUMPS; MOBILE ELECTRONICS; TECHNOLOGY PROGRESS; TEST VEHICLE; THROUGH-SILICON-VIA; WAFER LEVEL PACKAGE; WAFER LEVEL PROCESSING;

APPROXIMATION THEORY; COPPER; DESIGN; FLIP CHIP DEVICES; INFORMATION TECHNOLOGY; MICROPROCESSOR CHIPS; PACKAGING; SILICON WAFERS;

CHIP SCALE PACKAGES;

EID: 81355135283     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICEPT.2011.6067027     Document Type: Conference Paper

References (20)

1. P. Totta and R.P. Sopher, "SLT Device Metallurgy and its Monolithic Extensions," IBM J. of Res and Develop., 13, p. 226, May 1969.
2. L. F. Miller, "Controlled Collapse Reflow Chip Joining," IBM J. of Res and Develop., 13, p. 239, May 1969.
3. US Patent 3,429,040, "Method of Joining a Component to a Substrate", L. F. Miller, Feb 25, 1969.
4. J.U. Knickerbocker et al., "An Advanced Multichip Module for High-performance UNIX Servers," IBM Journal of Res and Develop., November 2002.
5. U.S. Patent 6,229,220, "Bump Structure, Bump Forming Method and Package Connecting Body", K. Saito and R. Shoji, May 8, 2001
6. U.S. Patent 6,578,754 "Pillar Connections for Semiconductor Chips and Method of Manufacture," Francisca Tung, June 17, 2003.
7. U.S. Patent 7,276,801 "Designs and Methods for Conductive Bumps" V.M. Dubin et al., October 2, 2007
8. A. Yeoh et al., "Copper Die Bumps (First Level Interconnect) and Low-K Dielectrics in 65nm High Volume Manufacturing," 56th ECTC, p. 1611, San Diego, CA, 2006.
9. B. Ebersberger and C. Lee, "Cu Pillar Bumps as a Lead-free Drop-in Replacement for Solder-Bumped, Flip-Chip Interconnects," 2008 ECTC
10. B. K. Appelt et al., "Next Generation fcCSP Packaging," ICEP Japan, April 14, 2011.
11. M. Gerber et al., "Next Generation Fine Pitch Cu Pillar Technology-Enabling Next Generation Silicon Nodes," 2011 ECTC, p. 612, Orlando, FL
12. W. Flack et al., "Thick Copper Pillar Bump Fabrication," ELECTROIQ Advanced Packaging
13. U.S. Patent 7,902,666, "Flip chip device having soldered metal posts by surface mounting," H.H. Hsu and J.C. Hsu, March 8, 2011.
14. H. Noma et al., "Wettability and Reliability on Double Side Assembly with MPS-C2 Flip Chip Technology," 2009 ICEP, April 16, Japan.
15. "Elpida Begins Sample Shipments of DDR3 SDRAM (x32) Based on TSV Stacking Technology," Elpida New Release, June 27, 2011.
16. "Samsung Develops Mobile DRAM with Wide I/O Interface using 50 nanometer Process Technology," I-Micronews, Feb 23, 2011.
17. Y.S. Lai et al., "Reliability Designs for 40nm ELK Flip Chip Packages with Copper Pillar Bumps," 2011 ICEP, Japan, April 13, 2011
18. A. Syed et al., "Cu Pillar and u-bump Electromigration Reliability and Comparison with High Pb, SnPb, and SnAg bumps," 2011 ECTC, June 3, Orlando, FL
19. E. J. Vardaman et al., "2010-11 Flip Chip and WLP: Market Projections and New Development," TechSearch International, November 2010.
20. Yole Development, "Flip-Chip: Technologies, Applications, Market Report-April, 2011".