A 4-GHz all digital fractional-N PLL with low-power TDC and big phase-error compensation

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2011, Pages

  Lee, Ja Yol ^a   Park, Mi Jeong ^a   Mhin, Byonghoon ^a   Kim, Seong Do ^a   Park, Moon Yang ^a   Yu, Hyunku ^a  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALL DIGITAL; ALL-DIGITAL PLL; CHANNEL SWITCHING; DYNAMIC POWER; FRACTIONAL-N; LOW POWER; OPERATION MODE; OUTPUT BITS; PHASE ERROR; REFERENCE CLOCK; TIMING SKEW;

CLOCKS; DIGITAL INTEGRATED CIRCUITS; FREQUENCY HOPPING; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATION; JITTER;

ERROR COMPENSATION;

EID: 80455145097     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2011.6055303     Document Type: Conference Paper

References (5)

1. R. B. Staszewski et al., "All-digital PLL and transmitter for mobile phones," IEEE J. Solid-State Circuits, no. 12, pp.2469-2482, 2005.
2. P. Y. Wang et al., "A digital intensive fractional-N PLL and all-digital self-calibration schemes," IEEE J. Solid-State Circuits, no. 8, pp.2182-2192, 2009.
3. H. H. Chang et al., "A 320fs-RMS-jitter and 300kHz-BW all-digital fractional-N PLL with self-corrected TDC and fast temperature tacking loop for WiMax/WLAN 11ns," in VLSI Symp. Dig. Tech. Papers, 2009, pp. 188-189.
4. A. Ravi et al., "A 9.2-12GHz 90nm digital fractional-N synthesizer with stochastic TDC calibration and -35/-41dBc integrated phase noise in the 5/2.5GHz bands," in VLSI Symp. Dig. Tech. Papers, 2010, pp. 143-144.
5. T. Tokairin et al., "A 2.1-to-2.8GHz low-phase-noise all-digital frequency synthesizer with a time-windowed time-to-digital converter,"IEEE J. Solid-State Circuits, vol. 45, no. 12, pp.2582-2590, 2010