A 320fs-RMS-jitter and 300kHz-BW all-digital fractional-N PLL with self-corrected TDC and fast temperature tacking loop for WiMax/WLAN 11n

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 188-189

  Chang, Hsiang Hui ^a   Fu, Chia Huang ^a   Chiu, Monty ^a  

^a MEDIATEK INC   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR FREE OPERATIONS; FRACTIONAL-N; META-STABLE; OPERATIONAL TEMPERATURE; SETTLING TIME; SMALL CHIP AREA; TIMING RESOLUTIONS; TRACKING LOOP; WIDE DYNAMIC RANGE;

JITTER; PHASE LOCKED LOOPS;

VLSI CIRCUITS;

EID: 70449382285     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. R. B. Staszewski, et. al., "All-Digital PLL and Transmitter for Mobile Phones," IEEE Journal of Solid-State Circuits, vol. 40, No. 12, pp. 2469 - 2482, Dec. 2005.
2. C. M. Hsu, et. al., "A Low-Noise, Wide-BW 3.6GHz Digital σδ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation," ISSCC Dig. Tech. Papers, pp. 340-341, 2008
3. H. H. Chang et. al., "A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE," ISSCC Dig. Tech. Papers, pp. 200-201, 2008.
4. M. Lee et. al., "A 9b, 1.25ps Resolution Coarse-Fine Time-to-Digital Converter in 90nm CMOS that Amplifies a Time Residue," Dig. Symp. VLSI Circuits, pp. 168-169, 2007