22-nm-node technology active-layer patterning for planar transistor devices

Journal of Micro/Nanolithography, MEMS, and MOEMS

Volumn 9, Issue 1, 2010, Pages

  Kim, Ryoung Han ^a   Holmes, Steven ^b   Halle, Scott ^b   Dai, Vito ^a   Meiring, Jason ^b   Dave, Aasutosh ^c   Colburn, Matthew E ^a   Levinson, Harry J ^a  

^a IBM MICROELECTRONICS   (United States)

^b IBM RESEARCH   (United States)

^c MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

22 nm technology; Design for manufacturability; Resolution enhancement technique; Static random access memory; Two dimensional feature

Indexed keywords

LITHOGRAPHY; MACHINE DESIGN; PRINTING; REFRACTIVE INDEX; TECHNOLOGY; TRANSISTORS;

22-NM TECHNOLOGY; DESIGN FOR MANUFACTURABILITY; RESOLUTION ENHANCEMENT TECHNIQUE; STATIC RANDOM ACCESS MEMORY; TWO-DIMENSIONAL FEATURES;

STATIC RANDOM ACCESS STORAGE;

EID: 80455131315     PISSN: 19325150     EISSN: 19325134     Source Type: Journal    
DOI: 10.1117/1.3302125     Document Type: Article

References (6)

1. 2 6T-SRAM Cell," in Tech. Dig. - Int. Electron Devices Meet., pp. 625-628 (2008).
2. C.-M. Lim, S.-M. Kim, T.-S. Eom, S.-C. Moon, and K.-S. Shin, "Diffraction analysis of customized illumination technique," Proc. SPIE 5377, pp. 1297-1304 (2004).
3. A. Rosenbluth, S. Bukofsky, M. Hibbs, K. Lai, A. Molless, R. N. Singh, and A. K. Wong, "Optimum mask and source patterns to print a given shape," Proc. SPIE 4346, 486-502 (2001).
4. R. Socha, X. Shi, and D. LeHoty, "Simultaneous source mask optimization (SMO)," Proc. SPIE 5853, 180-193 (2005). (Pubitemid 41744663)
5. D. Aasutosh and K. Ryoung-han, "Pushing the limits of RET with different illumination methods," Proc. SPIE 7274, 72741C (2009).
6. V. Farys, S. Warrick, C. Chaton, and J.-D. Chapon, "ARC stack development for hyper-NA imaging," Proc. SPIE 6520, 65204O (2007).