Impact of NMOS/PMOS imbalance in ultra-low voltage CMOS standard cells

2011 20th European Conference on Circuit Theory and Design, ECCTD 2011

Volumn , Issue , 2011, Pages 536-539

  Alioto, Massimo ^a,b  

^a UNIVERSITY OF SIENA   (Italy)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL MODEL; DESIGN CONSIDERATIONS; GATE SWITCHING; HIGH VARIABILITY; LEAKAGE ENERGIES; PROBABILITY DENSITIES; QUANTITATIVE MODELS; STANDARD CELL; SUPPLY VOLTAGES; ULTRALOW VOLTAGE; VLSI SYSTEM;

DESIGN; ELECTRIC BATTERIES; MATHEMATICAL MODELS; PROBABILITY DENSITY FUNCTION; VLSI CIRCUITS;

CIRCUIT THEORY;

EID: 80155143135     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECCTD.2011.6043407     Document Type: Conference Paper

References (9)

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5. M. Alioto, "Ultra-Low Power VLSI Design Demystified and Explained: a Tutorial," in print on IEEE Trans. on Circuits and Systems - part I (invited extended paper).
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9. T. Kim, H. Eom, J. Keane, and C. Kim, "Utilizing reverse short channel effect for optimal subthreshold circuit design," in Proc. of ISLPED 2006, pp. 127-130, 2006.