Increasing minimum operating voltage (VDDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2008, Pages 117-122

  Niiyama, Taro ^a   Piao, Zhe ^a   Ishida, Koichi ^a   Murakata, Masami ^a,b   Takamiya, Makoto ^a   Sakurai, Takayasu ^a  

^a UNIVERSITY OF TOKYO   (Japan)

^b SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

Author keywords

Logic; Minimum operating voltage; Subthreshold; Variations

Indexed keywords

LOGIC GATES; LOW POWER ELECTRONICS; POWER ELECTRONICS; REVERSE OSMOSIS; SWITCHING CIRCUITS;

CMOS LOGIC GATES; EXPERIMENTAL VERIFICATIONS; GATE WIDTHS; LOGIC; LOWER LIMITS; MEASURED RESULTS; MINIMUM OPERATING VOLTAGE; RANDOM THRESHOLDS; RING OSCILLATORS; STAGE RING OSCILLATORS; SUBTHRESHOLD; SUBTHRESHOLD CURRENT MODELS; SUBTHRESHOLD LOGIC; SUPPLY VOLTAGES; VARIATIONS;

LOGIC CIRCUITS;

EID: 57549091208     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1393921.1393952     Document Type: Conference Paper

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