Improving the immunity of smart power integrated circuits by controlling RF substrate coupling

IEEE International Symposium on Electromagnetic Compatibility

Volumn , Issue , 2011, Pages 45-50

  Schröter, Philipp ^a   Jahn, Stefan ^b   Klotz, Frank ^b  

^a ILMENAU UNIVERSITY OF TECHNOLOGY   (Germany)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMOTIVE APPLICATIONS; BCD TECHNOLOGY; ON-WAFER; SUBSTRATE COUPLINGS; TEST STRUCTURE;

ELECTROMAGNETIC COMPATIBILITY; ELECTROMAGNETIC PULSE; ELECTROMAGNETISM; INTEGRATION; SUBSTRATES;

POWER INTEGRATED CIRCUITS;

EID: 80054766210     PISSN: 10774076     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISEMC.2011.6038282     Document Type: Conference Paper

References (12)

1. J. M. Redoute and M. Steyaert "EMC of Analog Integrated Circuits", Springer, Berlin, November 2009.
2. M. Ramdani, E. Sicard, S. B. Dhia, J. Catrysse, "Towards an EMC roadmap for integrated Circuits", 2008 Asia Pacific Symposium & 19th International Zurich Symposium on Electromagnetic Compatibility, pp. 8-11, May 2008, Singapore
3. E. Orietti, N. Montemezzo, S. Buso, G. Meneghesso, A. Neviani, G. Spiazzi, "Reducing the EMI Susceptibility of a Kujik Bandgap", in: IEEE Transactions on Electromagnetic Compatibility, pp. 876-886, vol. 50, no. 4, November 2008
4. J.-M. Redoute, M. Steyaert, "An EMI Resisting LIN Driver in 0.35-micron High-Voltage CMOS", in: IEEE Journal of Solid State Circuits, pp. 1574-1582, vol. 42, no. 7, July 2007 (Pubitemid 47000222)
5. P. Schroeter, F. Klotz, "On Chip Filtering Versus Layout Techniques to Reduce RF Coupled Disturbances", in 2010 IEEE International Symposium on Electromagnetic Compatibility, pp., Fort Lauderdale, July 2010
6. W. Sansen, "Analog Design Essentials", Springer, 2006
7. A. Andreini, C. Contiero, P. Galbiati, "A New Integrated Silicon Gate Technology Combining Bipolar Linear, CMOS Logic, and DMOS Power Part", IEEE Transactions on ElectronDevices, vol. 33, no.12, December 1986
8. W. Sansen, "Distortion in Elementary Transistor Circuits", in: IEEE Transactions on Circuits an Systems-Analog and Digital Signal Processing, vol. 46, no. 3, pp. 315-325, March 1999
9. M. Nagata, J. Nagai, K. Hijikata, T. Morie, A. Iwata, "Physical Design Guides for Substrate Noise Reduction in CMOS Digital Circuits", in: IEEE Journal of Solid-State Circuits vol. 36, no. 3, pp. 539-549, March 2001 (Pubitemid 32302996)
10. M. van Heijningen, M. Badaroglu, S. M. Donnay, ,H. J. D. Man, G. G. E. Gielen, "Substrate Noise Generation in Complex Digital Systems: Efficient Modeling and Simulation Methodology and Experimental Verification", in: IEEE Journal of Solid-State-Circuits, vol. 37, no. 8, pp. 1065-1072, August 2001
11. Generic IC EMC Test Specification Version 1.2, Bosch, Infineon, Siemens VDO (BISS), 2004-2007
12. IEC 62132-4 Ed. 1 2005, "Integrated Circuits-Measurement of Electromagnetic Immunity-150kHz to 1GHz-Part 4: Direct RF Power Injection Method"