Implementation techniques of high-order FFT into low-cost FPGA

Midwest Symposium on Circuits and Systems

Volumn , Issue , 2011, Pages

  Ouerhani, Yousri ^a   Jridi, Maher ^a   Alfalou, A ^a  

^a Laboratoire L at bISEN   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK CYCLES; FFT ALGORITHM; FPGA IMPLEMENTATIONS; HIGH-ORDER; IMPLEMENTATION TECHNIQUES; IP CORE; KNOW-HOW; LOW AREA; RADIX-4; VLSI ARCHITECTURES; VLSI STRUCTURES;

FAST FOURIER TRANSFORMS; OPTIMIZATION; TECHNOLOGY TRANSFER;

VLSI CIRCUITS;

EID: 80053652899     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2011.6026390     Document Type: Conference Paper

References (7)

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3. H. Sorensen, M. Heindeman, and C. Burrus, On computing the split-radix FFT, IEEE Trans. Acoustics, Speech, Signal Process, vol.34, pp. 152-156, 1986.
4. K. Maharatna, E. Grass, and Ulrich Jagldhold, A 64-Point Fourier Transform Chip for High-Speed Wireless LAN Application Using OFDM, IEEE J. Solid-State Circuits, vol. 39, pp. 484-493, March 2004.
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6. M. Jridi and A. Alfalou, A Low-Power, High-Speed DCT architecture for image compression: principle and implementation, in Proc. VLSI Syst. in Chip Conf (VLSI-SoC), pp. 304-309, Sept 2010.
7. M. Jridi and A. Alfalou, Direct Digital Frequency Synthetizer with CORDIC Algorithm and Taylor Series Approximation for Digital Receivers, Euro Journal of Scientific Research, vol. 30, No. 4, pp. 542-553, 2009.