Failure modes and robustness of SiC JFET transistors under current limiting operations

Proceedings of the 2011 14th European Conference on Power Electronics and Applications, EPE 2011

Volumn , Issue , 2011, Pages

  Bouarroudj Berkani, Mounira ^a   Lefebvre, Stéphane ^a   Othman, Dhouha ^a   Sabrine, Sabrine Moumen ^a,b   Khatir, Zoubir ^b   Salah, Tarek Ben ^c  

^a UNIVERSITÉ PARIS SACLAY   (France)

^b UNIVERSITÉ GUSTAVE EIFFEL   (France)

^c UNIVERSITY OF TUNIS EL MANAR   (Tunisia)

Author keywords

Current limiter; JFET; Power semiconductor; Robustness; Short circuit; Silicon Carbide

Indexed keywords

AGEING TESTS; CURRENT LIMITATION; CURRENT LIMITING OPERATIONS; EXPERIMENTAL TEST; ON-STATE RESISTANCE; POWER SEMICONDUCTOR; SATURATION CURRENT; SHORT CIRCUIT; SHORT CIRCUIT MODE; THERMAL SIMULATIONS;

COMPUTER SIMULATION; JUNCTION GATE FIELD EFFECT TRANSISTORS; LIMITERS; POWER ELECTRONICS; SEMICONDUCTING SILICON COMPOUNDS; SILICON CARBIDE; TESTING; TRANSISTORS;

FAILURE ANALYSIS;

EID: 80053478610     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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