Automated mapping for reconfigurable single-electron transistor arrays

Proceedings - Design Automation Conference

Volumn , Issue , 2011, Pages 878-883

  Chen, Yung Chih ^a   Eachempati, Soumya ^b   Wang, Chun Yao ^a   Datta, Suman ^c   Xie, Yuan ^c   Narayanan, Vijaykrishnan ^c  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b INTEL CORPORATION   (United States)

^c The Pennsylvania State University   (United States)

Author keywords

Automatic synthesis; binary decision diagram; single electron transistor

Indexed keywords

AUTOMATION; BINARY DECISION DIAGRAMS; BOOLEAN FUNCTIONS; CAPACITANCE MEASUREMENT; FIELD EFFECT TRANSISTORS; LOGIC SYNTHESIS; MAPPING; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE;

AUTOMATED MAPPING; AUTOMATED SYNTHESIS; AUTOMATIC SYNTHESIS; EFFECTIVENESS AND EFFICIENCIES; LOW-POWER DEVICES; POWER REDUCTIONS; RECONFIGURABLE; RECONFIGURABLE LOGIC;

SINGLE ELECTRON TRANSISTORS;

EID: 80052647588     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2024724.2024920     Document Type: Conference Paper

References (12)

1. R. Bryant, "Graph-based Algorithms for Boolean Function Manipulation," IEEE Trans. Computers, vol. 35, pp. 677-691, Aug. 1986. (Pubitemid 16629996)
2. S. Eachempati, V. Saripalli, V. Narayanan, and S. Datta, "Recongurable Bdd-based Quantum Circuits," in Proc. Int. Symp. on Nanoscale Architectures, 2008, pp. 61-67.
3. H. Hasegawa and S. Kasai, "Hexagonal Binary Decision Diagram Quantum Logic Circuits Using Schottky In-Plane and Wrap Gate Control of GaAs and InGaAs Nanowires," Physica E: Low-dimensional Systems and Nanostructures, vol. 11, pp. 149-154, Oct. 2001. (Pubitemid 32951499)
4. S. Kasai, M. Yumoto, and H. Hasegawa, "Fabrication of GaAs-based Integrated 2-bit Half and Full Adders by Novel Hexagonal BDD Quantum Circuit Approach," in Proc. Int. Symp. on Semiconductor Device Research, 2001, pp. 622-625.
5. M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual: For System-on-Chip Design, Springer, 2007.
6. S. W. Keckler, K. Olukotun, and H. P. Hofstee, Multicore Processors and Systems, Springer, 2009.
7. C. Piguet, Low-power CMOS Circuits: Technology, Logic Design and CAD Tools, CRC Press, 2006.
8. V. Saripalli, L. Liu, S. Datta, and V. Narayanan, "Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits", Journal of Low Power Electronics (JOLPE), vol. 6, pp. 415-428, 2010.
9. F. Somenzi, CUDD: CU decision diagram package - release 2.4.2, 2009. http://vlsi.colorado.edu/~fabio/CUDD/
10. S. Yang, "Logic Synthesis and Optimization Benchmarks, Version 3.0," Tech. Report, Microelectronics Center of North Carolina, 1991.
11. http://embedded.eecs.berkeley.edu/pubs/downloads/ espresso/index.htm
12. http://www.intel.com/go/terascale/