Mutation analysis for SystemC designs at TLM

LATW 2011 - 12th IEEE Latin-American Test Workshop

Volumn , Issue , 2011, Pages

  Guarnieri, Valerio ^a   Bombieri, Nicola ^a   Pravadelli, Graziano ^a   Fummi, Franco ^a   Hantson, Hanno ^b   Raik, Jaan ^b   Jenihhin, Maksim ^b   Ubar, Raimund ^b  

^a UNIVERSITY OF VERONA   (Italy)

^b TALLINN UNIVERSITY OF TECHNOLOGY   (Estonia)

Author keywords

mutation analysis; RTL; SystemC; TLM

Indexed keywords

ABSTRACTION LEVEL; ANALYSIS PROCESS; DIGITAL SYSTEM; HARDWARE DESIGN; MUTATION ANALYSIS; MUTATION OPERATORS; REGISTER-TRANSFER LEVEL; RTL; SPEED-UPS; SYSTEMC; SYSTEMC DESIGN; TEST-BENCH; TLM; TRANSACTION LEVEL MODELING;

COMPUTER SOFTWARE SELECTION AND EVALUATION; LOGIC DESIGN; MULTIPROCESSING SYSTEMS;

SOFTWARE TESTING;

EID: 80052620551     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LATW.2011.5985925     Document Type: Conference Paper

References (14)

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