Using runtime activity to dynamically filter out inefficient data prefetches

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 6852 LNCS, Issue PART 1, 2011, Pages 338-350

  Gamoudi, Oussama ^a   Drach, Nathalie ^a   Heydemann, Karine ^a  

^a UNIVERSITÉ PIERRE ET MARIE CURIE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DATA-PREFETCHING; HARDWARE COUNTERS; MEMORY PRESSURE; NEGATIVE IMPACTS; PERFORMANCE DEGRADATION; PERFORMANCE IMPROVEMENTS; PREFETCHES; PREFETCHING; RUNTIMES; SIDE EFFECT;

PARALLEL PROCESSING SYSTEMS;

EID: 80052387747     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-23400-2_31     Document Type: Conference Paper

References (14)

1. Intel 64 and IA-32 Architectures Optimization Reference Manual. Intel Corporation (2009)
2. Binkert, N.L., Dreslinski, R.G., Hsu, L.R., Lim, K.T., Saidi, A.G., Reinhardt, S.K.: The m5 simulator: Modeling networked systems. IEEE Micro 25(1), 52-60 (2006)
3. Dahlgren, F., Dubois, M., Stenstrm, P.: Sequential hardware prefetching in shared-memory multiprocessors. IEEE Trans. Parallel Distrib. Syst. 25(1), 733-746 (1995)
4. Fu, J.W.C., Patel, J.H., Janssens, B.L.: Stride directed prefetching in scalar processors. In: MICRO 25: Proceedings of the 25th Annual International Symposium on Microarchitecture, pp. 102-110. IEEE Computer Society Press, Los Alamitos (1992)
5. Hu, Z., Kaxiras, S., Martonosi, M.: Timekeeping in the memory system: predicting and optimizing memory behavior. In: ISCA 2002: Proceedings of the 29th Annual International Symposium on Computer Architecture, pp. 209-220. IEEE Computer Society, Washington, DC, USA (2002)
6. Lai, A.-C., Fide, C., Falsafi, B.: Dead-block prediction & dead-block correlating prefetchers. In: ISCA 2001: Proceedings of the 28th Annual International Symposium on Computer Architecture, pp. 144-154. ACM, New York (2001)
7. Mutlu, O., Kim, H., Armstrong, D.N., Patt, Y.N.: Cache filtering techniques to reduce the negative impact of useless speculative memory references on processor performance. In: SBAC-PAD 2004: Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing, pp. 2-9. IEEE Computer Society Press, Los Alamitos (2004)
8. Nesbit, K.J., Dhodapkar, D., Smith, J.E.: Ac/dc: An adaptive data cache prefetcher. In: PACT 2004: Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques, pp. 135-145. IEEE Computer Society, New York (2004)
9. Perez, D.G., Gilles, M., Temam, O.: Microlib: A case for the quantitative comparison of micro-architecture mechanisms. In: MICRO 37: Proceedings of the 37th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 43-54. IEEE Computer Society, New York (2004)
10. Saavedra, R.H., Park, D.: Improving the effectiveness of software prefetching with adaptive execution. In: PACT 1996: Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques, p. 68. IEEE Computer Society, Washington, DC, USA (1996)
11. Smith, A.J.: Cache memories. Computing Surveys 14(3) (1982)
12. Srinath, S., Mutlu, O., Kim, H., Patt, Y.N.: Feedback directed prefetching: Improving the performance and bandwidth-efficiency of hardware prefetchers. In: HPCA 2007: Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture, pp. 63-74. IEEE Computer Society, Washington, DC, USA (2007)
13. Srinivasan, V., Davidson, E.S., Tyson, G.S.: A prefetch taxonomy. IEEE Trans. Comput. 53(2), 126-140 (2004)
14. Zhuang, X., Lee, H.-H.S.: Reducing cache pollution via dynamic data prefetch filtering. IEEE Trans. Comput. 56(1), 18-31 (2007)