FPGA based packet splitter implementation using mixed design flow

Elektronika ir Elektrotechnika

Volumn , Issue 8, 2008, Pages 15-18

  Shinde, S A ^a   Shelake, V G ^a   Kamat, R K ^a  

^a SHIVAJI UNIVERSITY   (India)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 79961076546     PISSN: 13921215     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (8)

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2. Saraswathi Sachidananda, Srividya Gopalan, Sridhar Varadarajan. Hardware-Software Hybrid Packet Processing for Intrusion Detection Systems. -Springer. -2005. -Vol. 3802/2005.
3. David V. Schuehler, John W. Lockwood. TCP Splitter: A TCP/IP Flow Monitor in Reconfigurable Hardware // IEEE Micro. -January/February 2003. -Vol. 23, No. 1. -P. 54-59.
4. Bertozzi D., Jalabert A., Murali S., Tamhankar R., Stergiou S., Benini L., de Micheli G. NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip. -2005.
5. Bolotin E., Cidon I., Ginosar R., Kolodny A. QNoC: QoS Architecture and Design Process for Networks on Chip // JSA. -Feb 2004.
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7. Moraes F., Calazans N., Mello A., Möller L., Ost L. Hermes: An Infrastructure for Low Area Overhead Packetswitching Networks on Chip, Integration // VLSI Journal. -Oct. 2004.
8. Roman Gindin, Israel Cidon, Idit Keidar. NoC-Based FPGA: Architecture and Routing. Accessed at: http:// www.ee.technion.ac.il/matrics/papers/NoCBased% 20FPGA.pdf. Retrieved on March 1, 2008.