Cu plating of through-si vias for 3D-stacked integrated circuits

Materials Research Society Symposium Proceedings

Volumn 1112, Issue , 2009, Pages 159-164

  Radisic, Aleksandar ^a   Lühn, Ole ^a,b   Swinnen, Bart ^a   Bender, Hugo ^a   Drijbooms, Chris ^a   Doumen, Geert ^a   Kellens, Kristof ^a   Ruythooren, Wouter ^a   Vereecken, Philippe M ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTROCHEMICAL MONITORING; IN-SITU; MANUFACTURING COST; POLISHING TIME; TA FILMS; THROUGH SILICON VIAS;

COPPER; INTEGRATED CIRCUITS; PLATING; TANTALUM; THREE DIMENSIONAL;

THIN FILM CIRCUITS;

EID: 70449567548     PISSN: 02729172     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. O. Lühn, J.-P. Celis, C. Van Hoof, K. Baert, and W. Ruythooren, ECS Transactions, 6 (8), 2007, 123-133.
2. th, Lake Buena Vista, 27-30 May, pp. 866-870, 2008.
3. A. Radisic, G. Oskam, and P. C. Searson, J. Electrochem. Soc., 151 (2004), C369-C374.
4. P. M. Vereecken, R. A. Binstead, H. Deligianni, and P. C. Andricacos, IBM J. Res. Dev., 49 (2005), 3-18.
5. Y. Cao, P. Taephaisitphongse, R. Chalupa, A. C. West, J. Electrochem. Soc., 148 (2001), C466-C472.
6. T. P. Moffat, D. Wheeler, S.-K. Kim, and D. Josell, J. Electrochem. Soc., 153 (2006), C127-C132.