Towards highly parallel event processing through reconfigurable hardware

7th International Workshop on Data Management on New Hardware, DaMoN 2011 - In Conjunction with ACM SIGMOD/PODS Conference

Volumn , Issue , 2011, Pages 27-32

  Sadoghi, Mohammad ^a   Singh, Harsh ^a   Jacobsen, Hans Arno ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMIC LANGUAGES; COMPUTER HARDWARE DESCRIPTION LANGUAGES; ECONOMIC AND SOCIAL EFFECTS; RECONFIGURABLE HARDWARE;

APPLICATION REQUIREMENTS; DEGREE OF PARALLELISM; EVENT PROCESSING; HIGH FREQUENCY HF; HIGH-LOW; HIGHLY PARALLELS; LOW LATENCY; PROCESSING PLATFORM; PUBLISH/SUBSCRIBE SYSTEM; TORONTO;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 79960155352     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1995441.1995445     Document Type: Conference Paper

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