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Volumn 3, Issue 1, 2010, Pages 660-669

Complex event detection at wire speed with FPGAs

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEX NETWORKS; DATA COMMUNICATION SYSTEMS; DATA HANDLING;

EID: 79957818631     PISSN: None     EISSN: 21508097     Source Type: Conference Proceeding    
DOI: 10.14778/1920841.1920926     Document Type: Article
Times cited : (73)

References (21)
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    • Agrawal, J.1    Diao, Y.2    Gyllstrom, D.3    Immerman, N.4
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    • Kickfire
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    • Compiling PCRE to FPGA for accelerating SNORT IDS
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    • A. Mitra, W. Najjar, and L. Bhuyan. Compiling PCRE to FPGA for accelerating SNORT IDS. In ANCS'07, New York, NY, USA, 2007.
    • (2007) ANCS'07
    • Mitra, A.1    Najjar, W.2    Bhuyan, L.3
  • 11
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    • Boosting XML Filtering Through a Scalable FPGA-Based Architecture
    • Asilomar, CA, USA
    • A. Mitra, M. R. Vieira, P. Bakalov, V. J. Tsotras, and W. A. Najjar. Boosting XML Filtering Through a Scalable FPGA-Based Architecture. In CIDR'09, Asilomar, CA, USA, 2009.
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    • Mitra, A.1    Vieira, M.R.2    Bakalov, P.3    Tsotras, V.J.4    Najjar, W.A.5
  • 12
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    • Streams on Wires-A Query Compiler for FPGAs
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    • R. Müller, J. Teubner, and G. Alonso. Streams on Wires - A Query Compiler for FPGAs. In VLDB'09, Lyon, France, 2009.
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    • Müller, R.1    Teubner, J.2    Alonso, G.3
  • 13
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    • Netezza Corp
    • Netezza Corp. http://www.netezza.com/.
  • 15
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    • Fast Regular Expression Matching Using FPGAs
    • Los Alamitos, CA, USA
    • R. Sidhu and V. Prasanna. Fast Regular Expression Matching Using FPGAs. In FCCM'01, Los Alamitos, CA, USA, 2001.
    • (2001) FCCM'01
    • Sidhu, R.1    Prasanna, V.2
  • 16
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    • FPGA Acceleration for the Frequent Item Problem
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    • J. Teubner, R. Müller, and G. Alonso. FPGA Acceleration for the Frequent Item Problem. In ICDE'10, Long Beach, CA, USA, 2010.
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    • Teubner, J.1    Müller, R.2    Alonso, G.3
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    • K. Thompson. Programming Techniques: Regular Expression Search Algorithm. Commun. ACM, 11(6), 1968.
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    • Thompson, K.1
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    • Compact Architecture for High-Throughput Regular Expression Matching on FPGA
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    • Y. Yang, W. Jiang, and V. Prasanna. Compact Architecture for High-Throughput Regular Expression Matching on FPGA. In ANCS'08, San Jose, CA, USA, 2008.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.