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Volumn 57, Issue 1, 2010, Pages 262-269

An ultralow-power 10-Gbits/s LVDS output driver

Author keywords

Impedance matching; Low power; Low voltage differential signaling (LVDS); Output drivers

Indexed keywords

BISMUTH ALLOYS; DATA TRANSFER; ENERGY GAP; IMPEDANCE MATCHING (ELECTRIC);

EID: 79958733748     PISSN: 15498328     EISSN: 15580806     Source Type: Journal    
DOI: 10.1109/TCSI.2009.2015721     Document Type: Article
Times cited : (19)

References (10)
  • 1
    • 84055168054 scopus 로고    scopus 로고
    • 4th ed. Nat. Semicond. Santa Clara, CA
    • "LVDS Owner's Manual, Design Guide, " 4th ed. Nat. Semicond., Santa Clara, CA, 2008.
    • (2008) LVDS Owner's Manual, Design Guide
  • 5
    • 0033224767 scopus 로고    scopus 로고
    • CML and ECL: Optimized design and comparison
    • Reg. Papers, Nov
    • M. Alioto and G. Palumbo, "CML and ECL: Optimized design and comparison, " IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 44, no. 11, pp. 1330-1341, Nov. 1999.
    • (1999) IEEE Trans. Circuits Syst. I , vol.44 , Issue.11 , pp. 1330-1341
    • Alioto, M.1    Palumbo, G.2
  • 6
    • 34547307497 scopus 로고    scopus 로고
    • Low power LVDS driver used in ADC systems
    • Circuit Technol
    • Q. Tang, Q. Yin, and J. Wu, "Low power LVDS driver used in ADC systems, " in Proc. 8th Int. Conf. Solid-State Integr. Circuit Technol., 2006, pp. 1664-1666.
    • (2006) Proc. 8th Int. Conf. Solid-State Integr. , pp. 1664-1666
    • Tang, Q.1    Yin, Q.2    Wu, J.3
  • 8
    • 9244225129 scopus 로고    scopus 로고
    • Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations
    • Nov
    • G. Esch Jr. and T. Chen, "Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations, " IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 11, pp. 1253-1257, Nov. 2004.
    • (2004) IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol.12 , Issue.11 , pp. 1253-1257
    • Esch, G.1    Chen, T.2
  • 9
    • 33645231427 scopus 로고    scopus 로고
    • Design of high-speed bipolar flip-flops for reduced clock loading
    • Mar. 16
    • T. E. Collins and S. I. Long, "Design of high-speed bipolar flip-flops for reduced clock loading, " Electron. Lett., vol. 42, no. 6, pp. 329-331, Mar. 16, 2006.
    • (2006) Electron. Lett. , vol.42 , Issue.6 , pp. 329-331
    • Collins, T.E.1    Long, S.I.2
  • 10
    • 84924270829 scopus 로고    scopus 로고
    • Jitter Fundamentals: The Reference Standard for Signal Integrity Analysis WAVECREST
    • Jitter Fundamentals: The Reference Standard for Signal Integrity Analysis WAVECREST.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.