A two-level caching mechanism for demand-based page-level address mapping in NAND flash memory storage systems

Real-Time Technology and Applications - Proceedings

Volumn , Issue , 2011, Pages 157-166

  Qin, Zhiwei ^a   Wang, Yi ^a   Liu, Duo ^a   Shao, Zili ^a  

^a HONG KONG POLYTECHNIC UNIVERSITY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

ADDRESS TRANSLATION; AVERAGE SYSTEM; CACHE CONFIGURATIONS; CACHE HIT RATIO; CACHING MECHANISM; FLASH TRANSLATION LAYER; HIT RATIO; NAND FLASH MEMORY; SPATIAL LOCALITY; SYSTEM RESPONSE TIME; TEMPORAL LOCALITY;

EMBEDDED SYSTEMS; MAPPING; NAND CIRCUITS; RANDOM ACCESS STORAGE; RESPONSE TIME (COMPUTER SYSTEMS);

FLASH MEMORY;

EID: 79957605744     PISSN: 10801812     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTAS.2011.23     Document Type: Conference Paper

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