An optical wavelength switching architecture for a high-performance low-power photonic NoC

Proceedings - 25th IEEE International Conference on Advanced Information Networking and Applications Workshops, WAINA 2011

Volumn , Issue , 2011, Pages 1-6

  Koohi, Somayyeh ^a   Shafaei, Alireza ^a   Hessabi, Shaahin ^a  

^a SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

Author keywords

NoC; Optics; Passive Router; Power Consumption; Wavelength Switching

Indexed keywords

ALL-OPTICAL ROUTER; AREA OVERHEAD; DATA STREAM; DATA TRANSMISSION DELAY; ELECTRICAL UNITS; ENERGY CONSUMPTION; LOW POWER; MULTICASTS; NOC; OPTICAL DATA; OPTICAL PACKETS; OPTICAL RESOURCES; OPTICAL WAVELENGTH; PASSIVE ROUTER; POWER CONSUMPTION; PROPOSED ARCHITECTURES; SIMULATION-BASED; TRAFFIC PATTERN; UNICAST; UNICAST PACKETS; WAVELENGTH ROUTING; WAVELENGTH SWITCHING; WAVELENGTH-SWITCHED;

ARCHITECTURE; COMPUTER ARCHITECTURE; DATA COMMUNICATION SYSTEMS; ENERGY UTILIZATION; FIBER OPTIC NETWORKS; MULTICASTING; MULTIPLEXING EQUIPMENT; ROUTERS; WAVELENGTH DIVISION MULTIPLEXING;

WAVELENGTH;

EID: 79957569616     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/WAINA.2011.23     Document Type: Conference Paper

References (18)

1. N. Kirman et al. "Leveraging Optical Technology in Future Bus-based Chip Multiprocessors," in IEEE/ACM Annual Intl. Symp. on Microarchitecture, pp. 492-503, 2006.
2. Y. Pan, P. Kumar, J. Kim, G. Memik, Y. Zhang, and A. Choudhary, "Firefly: Illuminating future network-on-chip with nanophotonics," in IEEE/ACM Intl. Symp. on Computer Architecture (ISCA), pp. 429-440, 2009.
3. D. Vantrease et al. "Corona: System Implications of Emerging Nanophotonic Technology," in IEEE/ACM Intl. Symp. on Computer Architecture (ISCA), pp. 153-164, 2008.
4. A. Shacham, K. Bergman, L. P. Carloni, "Photonic networks-on-chip for future generations of chip multi-processors," IEEE Trans. Comput., vol. 57, pp. 1-15, 2008.
5. S. Koohi, S. Hessabi, "Contention-Free on-Chip Routing of Optical Packets," in Intl. Symp. on Networks-on-Chip (NOCS), pp. 134-143, May 2009.
6. M. J. Cianchetti, J. C. Kerekes, and D. H. Albonesi, "Phastlane: A Rapid Transit Optical Routing Network," in IEEE/ACM Intl. Symp. on Computer Architecture (ISCA), pp. 441-450, 2009.
7. M. Briere et al., "System level assessment of an optical NoC in an MPSoC platform," in Design, Automation and Test in Europe (DATE), pp. 1084-1089, Mar. 2007.
8. M.P. Malumbres, J. Duato, and J. Torrellas, "An Efficient Implementation of Tree-Based Multicast Routing for Distributed Shared-Memory Multiprocessors," J. System Architecture, vol. 46, no. 11, pp. 1019-1032, 2000.
9. M. Coppola, R. Locatelli, G. Maruccia, L. Pieralisi, and M.D. Grammatikakis, "Spidergon: A NoC modeling paradigm," book chapter in Model Driven Engineering for Distributed Real-time Embedded Systems, ISBN: 1905209320, Aug. 2005.
10. P. Koonath, T. Indukuri, B. Jalali, " Add-drop filters utilizing vertically coupled microdisk resonators in silicon," J. Applied Physics Lett., vol. 86, pp. 091102-1-091102-3, Mar. 2005.
11. H. Gu, J. Xu, and Z. Wang, "A novel optical mesh network-on-chip for gigascale systems-on-chip," in IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS), pp. 1728-1731, 2008.
12. "OMNeT++ discrete event simulation system," available online at http://www.omnetpp.org/.
13. ITRS, "The international technology roadmap for semiconductors - 2007 edition," Available at http://public.itrs.net, 2007.
14. I.-W. Hsieh, X. Chen, J. I. Dadap, N. C. Panoiu, J. Richard M. Osgood, S. J. McNab, and Y. A. Vlasov, "Ultrafast-pulse self-phase modulation and third-order dispersion in si photonic wire-waveguides," Optics Express, vol. 14, no. 25, pp. 12380-12387, 2006.
15. R. Ho, "Wire scaling and trends," a presentation at MTO DARPA meeting, Sun Microsystems Laboratories, Jackson Hole, WY, Aug. 2006.
16. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, "The SPLASH-2 programs: Characterization and methodological considerations," in Intl. Symp. on Computer Architecture (ISCA), pages 24-36, 1995.
17. O'Connor, F. Gaffiot, "On-chip optical interconnect for low-power," in: E. Macii (Ed.), Ultra-Low Power Electronics and Design, Kluwer, Dordrecht, 2004.
18. M. Haurylau et al. "On-chip optical interconnect roadmap: Challenges and critical directions," IEEE J. Sel. Topics Quantum Electron, vol. 12, no. 6, pp. 1699-1705 , 2006.