Evaluating the potential of graphics processors for high performance embedded computing

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2011, Pages 709-714

  Mu, Shuai ^a   Wang, Chenxi ^a   Liu, Ming ^b   Li, Dongdong ^b   Zhu, Maohua ^a   Chen, Xiaoliang ^c   Xie, Xiang ^a   Deng, Yangdong ^a  

^a TSINGHUA UNIVERSITY   (China)

^b BEIHANG UNIVERSITY   (China)

^c INSTITUTE OF GEOLOGY AND GEOPHYSICS   (China)

Author keywords

DSP; Fermi; GFLOPS; GPU; HPEC benchmark; Multi core; parallel computing

Indexed keywords

DSP; FERMI; GFLOPS; GPU; HPEC BENCHMARK; MULTI CORE; PARALLEL COMPUTING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BENCHMARKING; DIGITAL INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSORS; EMBEDDED SOFTWARE; PARALLEL ARCHITECTURES; PROGRAM PROCESSORS; SIGNAL PROCESSING;

COMPUTER GRAPHICS EQUIPMENT;

EID: 79957562287     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (29)

1. H. J. Chao and B. Liu, "High Performance Switches and Routers," Wiley-Interscience, A John Wiley & Sons, INC., Publications, 2007.
2. S. Glisic and J. P. Makela, "Advanced Wireless Networks : 4G Technologies", IEEE Symposium on Spread Spectrum Techniques and Applications, pp. 442-446, Aug. 2006.
3. TI, High Performance DSP, TMS320C647x Multicore DSP http://focus.ti.com/ docs/prod/folders/print/tms320c6472.html.
4. Wikipedia, FLOPS, http://en.wikipedia.org/wiki/FLOPS.
5. NVidia Fermi Compute Architecture Whitepaper, http://www.nvidia.com/ content/PDF/fermi-white-papers/NVIDIA-Fermi-Compute-Architecture-Whitepaper.pdf.
6. NVidia, CUDA Programming Guide for CUDA Toolkit 3.1.1, http://developer.download.nvidia.com/compute/cuda/3-1/toolkit/docs/ NVIDIA-CUDA-C-ProgrammingGuide-3.1.pdf.
7. HPEC Challenge Benchmark Suite. http://www.ll.mit.edu/HPECchallenge/
8. GPGPU-Sim, http://www.ece.ubc.ca/~aamodt/gpgpu-sim/.
9. T. Jansen, B. R. Lipinski, N. Hanssen, and E. Keeve, "Fourier volume rendering on theGPU using a split-stream-FFT," in Proc. Vision,Modeling and Visualization Workshop, Stanford, pp. 395-403, Nov. 2004.
10. N. K. Govindaraju, S. Larsen, J. Gray, and D.Manocha, "A memory model for scientific algorithms on graphics processors," in Proc. SuperComputing, pp. 6-6, 2006.
11. Fialka, O. Cadik, "FFT and Convolution Performance in image Filtering on GPU", in Information Visualization, pp. 609-614, England, 2006.
12. S. M. Seitz, B. Curless, J. Diebel, D. Scharstein, and R. Szeliski, "A comparison and evaluation of multi-view stereo reconstruction algorithms," in Proc. IEEE Computer Society Conf. Computer Vision and Pattern Recognition (CVPR), New York, vol. 1, pp. 519-526, Nov. 2006.
13. J. Pettersson, "Radar Signal Processing with Graphics Processors (GPUs)", Master Thesis, Uppsala University, 2010. http://www.hpcsweden.se/ files/RadarSignalProcessingwithGraphicsProcessors.pdf.
14. A. Kerr, D. Campbell, M. Richards, "GPU Performance Assessment with the HPEC Challenge", HPEC Workshop in MIT Lincoln Laboratory, 2008.
15. CUDA FFT Library, www.nvidia.com/object/cuda-develop.html
16. CUDA SDK, http://developer.nvidia.com/object/cuda-3-1-downloads.html.
17. W. Coate and M. Arakawa, "Preliminary design review: Feature-aided tracking for the PCA integrated radar-tracker application", Project Report PCA-IRT-5, MIT Lincoln Laboratory, MA, October 2004.
18. J. Ming, X. J. Wang, R. S. He, Z. X. Chi, "An Efficient Fine-grained Parallel Genetic Algorithm Based on GPU-Accelerated", Network and Parallel Computing Workshops, pp. 855-862, October, 2007.
19. M. L. Wong and T. T. Wong, "Implementation of Parallel Genetic Algorithms on Graphics Processing Units", Intelligent and Evolutionary Systems Studies in Computational Intelligence, vol. 187, 2009.
20. Barcelona, "High Performance Genetic Programming on GPU", in Proc. of 2009 ICAC workshop on Bio-inspired algorithms for distributed systems, pp. 85-94, 2009.
21. A. S. David, R. J. Randall, J. H. William, P. M. Dwight, Vector, signal and image processing library(VSIPL) 1.3 application programmer's interface, Technical report, Georgia Tech Research Corporation, 2008, http://www.vsipl.org.
22. H. G. Gene and F. V. Charales, Matrix Computations, Johns Hopkins Universtiy Press, 3rd edtion, 1996
23. Kerr, D. Campbell and M. Richards, "QR decomposition on GPUs", in Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units, vol. 383, pp. 71-78, Washington, D.C. 2009.
24. V. Volkov and J. W. Dmmel, "Benchmarking GPUs to tune dense linear algebra", IEEE High Performance Computing, Networking, Storage and Analysis, pp. 1-11, 2008.
25. S. Lahabar, P.J. Narayanan, "Singular Value Decomposition on GPU using CUDA", IEEE Symposium on Parallel & Distributed Processing, pp. 1-10, May, 2009.
26. S. Mu, X. Y. Zhang, N. R. Zhang, J. X. Lu, Y. Deng and S. Zhang, "IP routing processing with graphic processors", Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 93-98, 2010.
27. C. Kim, J. Chhugani, N. Satish, E. Sedlar, A. D. Nguyen, et al. "Fast: Fast Architecture Sensitive Tree Search on Modern CPUs and GPUs", in Proc. of the 2010 international conference on Management of data, pp. 339-350, 2010.
28. ADSP-TS101 TigerSHARC 6U cPCI board, http://www.bittware.com/products/ hardware/dsp.cfm
29. Bakhoda, A. Yuan, G. L. Fung, W. W. L. Wong and H. Aamodt, "Analyzing CUDA Workloads Using a Detailed GPU Simulator", IEEE Symposium on Performance Analysis of Systems and Software, pp. 163-174, Boston MA, April 2009.