Statistical approach to design DRAM bitcell considering overlay errors

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7275, Issue , 2009, Pages

  Pyo, Yu Jin ^a   Kim, Dae Wook ^a   Park, Jai Kyun ^a   Doh, Ji Seong ^a   Kang, Hyun Jae ^a   Hong, Ji Suk ^a   Park, Chul Hong ^a   Lee, Sang Hoon ^a   Yoo, Moon Hyun ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

DRAM bitcell; Monte carlo simulation; Overlay specification; Parametric yield; Systematic yield

Indexed keywords

DRAM BITCELL; MONTE CARLO SIMULATION; OVERLAY SPECIFICATION; PARAMETRIC YIELD; SYSTEMATIC YIELD;

DYNAMIC RANDOM ACCESS STORAGE; HARDWARE; MACHINE DESIGN; MONTE CARLO METHODS; MOSFET DEVICES; SPECIFICATIONS;

ARCHITECTURAL DESIGN;

EID: 66749186325     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.815341     Document Type: Conference Paper

References (5)

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4. Kim, I. G., Park, S. H., Yoon, J. S., D-J Kim, J-Y Noh, J-H Lee, Y-S Kim, M-W Hwang, K-H Yang, J-S Park and K-S Oh, Electron Devices Meeting, IEDM Technical Digest. pp319- 322 (2005)
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