A 0.9V 1T1C SBT-based embedded non-volatile FeRAM with a reference voltage scheme and multi-layer shielded bit-line structure

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Yamaoka, Kunisato ^a   Iwanari, Shunichi ^a   Murakuki, Yasuo ^a   Hirano, Hiroshige ^a   Sakagami, Masahiko ^a   Nakakuma, Tetsuji ^a   Miki, Takashi ^a   Gohou, Yasushi ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIT-LINE STRUCTURES; SENSE AMPLIFIERS; SHUNT BIT-LINES; VOLTAGE DIFFERENCE;

AMPLIFIERS (ELECTRONIC); CAPACITANCE; CAPACITORS; ELECTRIC POTENTIAL; EMBEDDED SYSTEMS; MOBILE TELECOMMUNICATION SYSTEMS; MULTILAYERS; POLYSILICON; SENSITIVITY ANALYSIS;

RANDOM ACCESS STORAGE;

EID: 2442693931     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Y. Chung et al., "A 3.3-V 4-Mb Nonvolatile Ferroelectric RAM with a Selectively-Driven Double-Pulsed Plate Read/Write-Back Scheme," Symposium on VLSI Circuits Digest, pp. 97-98, Jun. 1999.
2. J. Yamada et al., "A Self-Reference Read Scheme for a 1T/1C FeRAM," Symposium on VLSI Circuits Digest, pp. 238-241, Jun. 1998.
3. H. Hirano et al., "2V/100ns 1T/1C Nonvolatile Ferroelectric Memory Architecture with Bitline-Driven Read Scheme & Non-Relaxation Reference Cell," Symposium on VLSI Circuits Digest, pp. 48-49, Jun. 1996.
4. T. Sumi et al., "A 0.9V Embedded Ferroelectric Memory for Microcontrollers," ISSCC Dig. Tech. Papers, pp.70-71, Feb. 1995.