A nonvolatile ferroelectric RAM with common plate folded bit-line cell and enhanced data sensing scheme

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 38-39

  Jeon, B G ^a   Choi, M K ^a   Song, Y ^a   Kim, K ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITANCE; CAPACITORS; DECODING; FERROELECTRIC DEVICES; PLATED WIRE STORAGE;

FERROELECTRIC RANDOM ACCESS STORAGE (FRAM);

RANDOM ACCESS STORAGE;

EID: 0035054708     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A 16kb ferroelectric nonvolatile memory with a bit parallel architecture
2. A 3.3-V 4-Mb nonvolatile ferroelectric RAM with a selectively-driven double-pulsed plate read/write-back scheme
3. A 0.5μm 3V 1T1C 1Mb FRAM with a variable reference bitline voltage scheme using a fatigue-free reference capacitor
4. A 256kb nonvolatile ferroelectric memory at 3V and 100ns
5. A 0.4μm 3.3V 1T1C 4Mb nonvolatile ferroelectric RAM with fixed bit-line reference voltage scheme and data protection circuit