A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI

Proceedings of the Custom Integrated Circuits Conference

Volumn 2005, Issue , 2005, Pages 527-530

  Hamada, Mototsugu ^a   Hara, Hiroyuki ^a   Fujita, Tetsuya ^a   Chen, Kong Teh ^a   Shimazawa, Takayoshi ^a   Kawabe, Naoyuki ^a   Kitahara, Takeshi ^a   Kikuchi, Yu ^a   Nishikawa, Tsuyoshi ^a   Takahashi, Masafumi ^a   Oowaki, Yukihito ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Clock gating; Flip flop; Low power

Indexed keywords

AUDIO SYSTEMS; DIGITAL CIRCUITS; ELECTRIC CLOCKS; PROBABILITY;

AUXILIARY CIRCUITS; CLOCK GATING; LOW POWER;

FLIP FLOP CIRCUITS;

EID: 33847101870     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2005.1568722     Document Type: Conference Paper

References (4)

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