Defect gallery and bump defect reduction in the self-aligned double patterning module

IEEE Transactions on Semiconductor Manufacturing

Volumn 24, Issue 2, 2011, Pages 145-150

  Cai, Cathy ^a   Padhi, Deenesh ^a   Seamons, Martin ^a   Bencher, Chris ^a   Ngai, Chris ^a   Kim, Bok Heon ^a  

^a APPLIED MATERIALS INC   (United States)

Author keywords

Bumps reduction; defect gallery; self aligned double patterning (SADP)

Indexed keywords

BASELINE PROCESS; BUMP DEFECTS; BUMPS REDUCTION; DATA COLLECTION; DEFECT CHARACTERIZATION; DOUBLE PATTERNING; FILM-DEPOSITION PROCESS; IMMERSION SCANNERS; IN-DEPTH STUDY; LINE STRUCTURES; MANUFACTURING SITES; NEW DIRECTIONS; POTENTIAL SOLUTIONS; SELF-ALIGNED; SELF-ALIGNED DOUBLE PATTERNING (SADP); UP TIME; WAFER FABRICATIONS;

PHOTOLITHOGRAPHY; SCANNING;

DEFECTS;

EID: 79955656801     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2011.2121096     Document Type: Conference Paper

References (4)

1. C. Bencher, Y. Chen, H. Dai, M. Warren, and H. Lior, "22 nm half-pitch patterning by CVD spacer self alignment double patterning (SADP)", in Proc. 21st SPIE Microlithography, vol. 6924. 2008, pp. 69244E-1-69244E-7.
2. A. Conley, D. Meshulach, G. Gichon, I. Dolev, R. Perlovitch, N. Landwer, C. Ngai, M.-P. Cai, and L. Miao, "From simulation to characterization: Integrated approach for self aligned double patterning defectivity", presented at ISSM 2008, Tokyo, Japan, Oct. 27-29, 2008, paper YE-O-109.
3. C. Ngai, "Manufacturing ready self-aligned double patterning for 3xnm Flash production", Sematech Litho Forum, May 13, 2008.
4. Y. Wed, "Formation mechanism of 193 nm immersion defects and defect reduction strategies", in Proc. 21st SPIE Microlithography, vol. 6923. 2008, pp. 69231Y-1-69231Y-9.