Configurable multiplier blocks for embedding in FPGAs

Electronics Letters

Volumn 34, Issue 7, 1998, Pages 638-639

  Haynes, S D ^a   Cheung, P Y K ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

IMAGE PROCESSING; LOGIC GATES; MULTIPLYING CIRCUITS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

LOGIC CIRCUITS;

EID: 0032473677     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19980501     Document Type: Article

References (8)

1. ATHANAS, P.M., and ABBOTT, A.L.: 'Real-time image processing on a custom computing platform', IEEE Comput., 1995, 28, (2), pp. 16-25
2. Altera Corporation: 'Ripple-carry adders in FLEX 8000 devices'. Application Brief 118, May 1994, Vers. 2
3. ALBAHARNA, O.T., CHEUNG, P.Y.K., and CLARKE, T.J.: 'On the viability of FPGA-based integrated coprocessors'. IEEE Symp. on FPGAs for Custom Computing Machines, 17-19 April 1996, pp. 206-215
4. ALBAHARNA, O.T., CHEUNG, P.Y.K., and CLARKE, T.J.: 'Area & time limitations of FPGA-based virtual hardware'. IEEE Proc. Int. Conf. on Computer Design: VLSI in computers and processors, 1994, pp. 184-189
5. HWANG, K.: 'Computer arithmetic principles, architecture, and design' (John Wiley & Sons, 1979), 1st edn., pp. 194-197
6. WALLACE, C.S.: 'A suggestion for fast multipliers', IEEE Trans. Electron. Comput., 1964, EC-13, pp. 14-17
7. BOOTH, A.D.: 'A signed binary multiplication technique', Q. J. Mech. Appl. Math., 1951, 4, (2), pp. 236-240
8. BAUGH, A.R., and WOOLEY, B.A.: 'A two's complement parallel array multiplication algorithm', IEEE Trans. Comput., 1973, C-22, (1-2), pp. 1045-1047