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Volumn , Issue , 2011, Pages 483-487

Issues and challenges in development of massively-parallel heterogeneous MPSOCS based on adaptable ASIPs

Author keywords

architecture synthesis; customizable ASIPs; embedded systems; heterogeneous multi processor system on chip (MPSoC); MPSoC and ASIP design automation

Indexed keywords

APPLICATION MAPPING; APPLICATION SPECIFIC INSTRUCTION SET PROCESSOR; ARCHITECTURE SYNTHESIS; ARTEMIS; COST EFFICIENCY; CUSTOMIZABLE; CUSTOMIZABLE ASIPS; DESIGN AND DEVELOPMENT; DESIGN METHOD; ELECTRONIC DESIGN AUTOMATION TOOLS; ELECTRONIC TECHNOLOGIES; EMBEDDED APPLICATION; EUROPEAN PROJECT; HETEROGENEOUS MULTI-PROCESSOR SYSTEM-ON-CHIP (MPSOC); HIGH DEMAND; INTEGRATED SYSTEMS; ISSUES AND CHALLENGES; MPSOC AND ASIP DESIGN AUTOMATION; MULTI PROCESSOR SYSTEMS; REAL-TIME COMPUTATIONS; SINGLE CHIPS; SYSTEM ARCHITECTURES;

EID: 79955048560     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PDP.2011.55     Document Type: Conference Paper
Times cited : (7)

References (8)
  • 3
    • 42949160106 scopus 로고    scopus 로고
    • Quality-driven model-based architecture synthesis for real-time embedded SoCs
    • DOI 10.1016/j.sysarc.2007.09.001, PII S138376210700121X
    • L. Jóźwiak and S.-A. Ong: Quality-driven Model-based Architecture Synthesis for Real-time Embedded SoCs, Journal of Systems Architecture, Vol. 54, No 3-4, 2008, pp. 349-368 (Pubitemid 351615327)
    • (2008) Journal of Systems Architecture , vol.54 , Issue.3-4 , pp. 349-368
    • Jozwiak, L.1    Ong, S.-A.2
  • 4
    • 70449635907 scopus 로고    scopus 로고
    • Modern development methods and tools for embedded reconfigurable systems - A survey
    • L. Jóźwiak, N. Nedjah and M. Figueroa: Modern Development Methods and Tools for Embedded Reconfigurable Systems - A Survey, Integration - the VLSI Journal, Vol. 43, No 1, 2010, pp. 1-33
    • (2010) Integration - The VLSI Journal , vol.43 , Issue.1 , pp. 1-33
    • Jóźwiak, L.1    Nedjah, N.2    Figueroa, M.3
  • 7
    • 34547397357 scopus 로고    scopus 로고
    • Synthesis of predictable networks-on-chip based interconnect architectures for chip multi-processors
    • S. Murali, D. Atienza, P. Meloni, S. Carta, L. Benini, G. De Micheli, L. Raffo. "Synthesis of Predictable Networks-on-Chip Based Interconnect Architectures for Chip Multi-Processors". IEEE Transactions On VLSI, Vol. 15, No 8, 2008, pp. 869 - 880
    • (2008) IEEE Transactions on VLSI , vol.15 , Issue.8 , pp. 869-880
    • Murali, S.1    Atienza, D.2    Meloni, P.3    Carta, S.4    Benini, L.5    De Micheli, G.6    Raffo, L.7


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.