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Volumn 7942, Issue , 2011, Pages

InP on SOI devices for optical communication and optical network on chip

Author keywords

[No Author keywords available]

Indexed keywords

CMOS CIRCUITS; CMOS COMPATIBILITY; CONTINUOUS WAVE; DIRECT BONDING; DIRECT MODULATION; DIRECTLY MODULATED; HETEROSTRUCTURES; HIGH PERFORMANCE COMPUTING; HIGH-SPEED COMMUNICATIONS; INGAAS PHOTODETECTORS; INNOVATIVE DESIGN; INP; INP SUBSTRATES; MICRODISK LASER; OFF-CHIP; OFF-CHIP COMMUNICATION; OPTICAL NETWORK ON CHIP; OPTICAL NETWORKS; OPTICAL POWER; OUTPUT POWER; RING RESONATOR; ROOM TEMPERATURE; SI DEVICES; SIDE MODE SUPPRESSION RATIOS; SILICON WAVEGUIDE; SOI DEVICES; SOI WAFERS; WAFER SCALE;

EID: 79953706291     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.878607     Document Type: Conference Paper
Times cited : (13)

References (14)
  • 10
    • 67449128189 scopus 로고    scopus 로고
    • Device requirements for optical interconnects to silicon chips
    • D. A. B. Miller, "Device Requirements for Optical Interconnects to Silicon Chips," Proc. IEEE, vol. 97, pp. 1166-1185 (2009).
    • (2009) Proc. IEEE , vol.97 , pp. 1166-1185
    • Miller, D.A.B.1
  • 11
    • 75749153228 scopus 로고    scopus 로고
    • Low-footprint optical interconnect on an SOI chip through heterogeneous integration of InP-based microdisk lasers and microdetectors
    • J. Van Campenhout et al. "Low-footprint optical interconnect on an SOI chip through heterogeneous integration of InP-based microdisk lasers and microdetectors," IEEE Photon. Technol. Lett., vol. 21, pp. 522-524, 2009.
    • (2009) IEEE Photon. Technol. Lett. , vol.21 , pp. 522-524
    • Van Campenhout, J.1
  • 12
    • 79953688806 scopus 로고    scopus 로고
    • CMOS compatible contacts and etching for InP-on-silicon active devices
    • San Francisco, September 11th
    • L. Grenouillet et al., "CMOS compatible contacts and etching for InP-on-silicon active devices," GFP conference, San Francisco, September 11th, 2009.
    • (2009) GFP Conference
    • Grenouillet, L.1
  • 13
    • 77954983229 scopus 로고    scopus 로고
    • III-V/silicon-on-insulator nanophotonic cavities for optical networks-on-chip
    • L. Liu et al., "III-V/silicon-on-insulator nanophotonic cavities for optical networks-on-chip," J. Nanosci. Nanotechnol., vol. 10, pp. 1461-1472, 2010
    • (2010) J. Nanosci. Nanotechnol. , vol.10 , pp. 1461-1472
    • Liu, L.1
  • 14
    • 79953703232 scopus 로고    scopus 로고
    • 200mm wafer scale III-V/SOI technology for all-optical network-on-chip and signal processing
    • to appear in IEEE publication
    • L. Liu et al., "200mm Wafer Scale III-V/SOI Technology for All-Optical Network-on-Chip and Signal Processing", Group IV Photonics Conference 2010, to appear in IEEE publication.
    • Group IV Photonics Conference 2010
    • Liu, L.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.