-
1
-
-
79952777822
-
System and method of maintaining coherency in a distributed communication system
-
U.S. Patent 7069361, Jun
-
J. M. Owen, M. D. Hummel, D. R. Meyer, and J. B. Keller, "System and method of maintaining coherency in a distributed communication system," U.S. Patent 7069361, Jun. 2006.
-
(2006)
-
-
Owen, J.M.1
Hummel, M.D.2
Meyer, D.R.3
Keller, J.B.4
-
2
-
-
70449693703
-
-
whitepaper, Jan. Online. Available
-
Intel, "An introduction to the Intel QuickPath interconnect," whitepaper, Jan. 2009. [Online]. Available: http://www.intel.com/technology/ quickpath/introduction.pdf
-
(2009)
An Introduction to the Intel QuickPath Interconnect
-
-
-
4
-
-
77951200277
-
Cache hierarchy and memory subsystem of the AMD opteron processor
-
Apr.
-
P. Conway, N. Kalyanasundharam, G. Donley, K. Lepak, and B. Hughes, "Cache hierarchy and memory subsystem of the AMD opteron processor," IEEE Micro, vol. 30, no. 2, pp. 16-29, Apr. 2010.
-
(2010)
IEEE Micro
, vol.30
, Issue.2
, pp. 16-29
-
-
Conway, P.1
Kalyanasundharam, N.2
Donley, G.3
Lepak, K.4
Hughes, B.5
-
5
-
-
79952809751
-
Computer System with Integrated Directory and Processor Cache
-
U.S. Patent 6868485, Mar
-
P. Conway, "Computer system with integrated directory and processor cache," U.S. Patent 6868485, Mar. 2005.
-
(2005)
-
-
Conway, P.1
-
7
-
-
79952805661
-
-
whitepaper, Online. Available
-
3Leaf Systems, "Next generation hybrid systems for HPC," whitepaper, 2009. [Online]. Available: http://www.3leafsystems.com/download/ 3leaf-wt-paper-Next-Gen-Hybrid-Sys%tems-for-HPC.pdf
-
(2009)
Next Generation Hybrid Systems for HPC
-
-
-
8
-
-
78649469883
-
Extending Hyper-Transport protocol for improved scalability
-
J. Duato, F. Silla, S. Yalamanchili, B. Holden, P. Miranda, J. Underhill, M. Cavalli, and U. Brning, "Extending Hyper-Transport protocol for improved scalability," in 1st Int'l Workshop on HyperTransport Research and Applications (WHTRA), Feb. 2009, pp. 46-53.
-
1st Int'l Workshop on HyperTransport Research and Applications (WHTRA), Feb. 2009
, pp. 46-53
-
-
Duato, J.1
Silla, F.2
Yalamanchili, S.3
Holden, B.4
Miranda, P.5
Underhill, J.6
Cavalli, M.7
Brning, U.8
-
9
-
-
20344401810
-
Horus: Large-scale symmetric multi-processing for opteron systems
-
Mar.
-
R. Kota and R. Oehler, "Horus: Large-scale symmetric multi-processing for opteron systems," IEEE Micro, vol. 25, no. 2, pp. 30-40, Mar. 2005.
-
(2005)
IEEE Micro
, vol.25
, Issue.2
, pp. 30-40
-
-
Kota, R.1
Oehler, R.2
-
10
-
-
0023795996
-
An evaluation of directory schemes for cache coherence
-
A. Agarwal, R. Simoni, J. L. Hennessy, and M. A. Horowitz, "An evaluation of directory schemes for cache coherence," in 15th Int'l Symp. on Computer Architecture (ISCA), May 1988, pp. 280-289.
-
15th Int'l Symp. on Computer Architecture (ISCA), May 1988
, pp. 280-289
-
-
Agarwal, A.1
Simoni, R.2
Hennessy, J.L.3
Horowitz, M.A.4
-
12
-
-
0036469676
-
Simics: A full system simulation platform
-
Feb.
-
P. S. Magnusson, et al, "Simics: A full system simulation platform," IEEE Computer, vol. 35, no. 2, pp. 50-58, Feb. 2002.
-
(2002)
IEEE Computer
, vol.35
, Issue.2
, pp. 50-58
-
-
Magnusson, P.S.1
-
13
-
-
33748870886
-
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
-
Sep.
-
M. M. Martin, et al, "Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset," Computer Architecture News, vol. 33, no. 4, pp. 92-99, Sep. 2005.
-
(2005)
Computer Architecture News
, vol.33
, Issue.4
, pp. 92-99
-
-
Martin, M.M.1
-
14
-
-
70049105948
-
GARNET: A detailed on-chip network model inside a full-system simulator
-
N. Agarwal, T. Krishna, L.-S. Peh, and N. K. Jha, "GARNET: A detailed on-chip network model inside a full-system simulator," in IEEE Int'l Symp. on Performance Analysis of Systems and Software (ISPASS), Apr. 2009, pp. 33-42.
-
IEEE Int'l Symp. on Performance Analysis of Systems and Software (ISPASS), Apr. 2009
, pp. 33-42
-
-
Agarwal, N.1
Krishna, T.2
Peh, L.-S.3
Jha, N.K.4
-
15
-
-
67649661466
-
-
HP Labs, Tech. Rep. HPL-2008-20, Apr.
-
S. Thoziyoor, N. Muralimanohar, J. H. Ahn, and N. P. Jouppi, "Cacti 5.1," HP Labs, Tech. Rep. HPL-2008-20, Apr. 2008.
-
(2008)
Cacti 5.1
-
-
Thoziyoor, S.1
Muralimanohar, N.2
Ahn, J.H.3
Jouppi, N.P.4
-
16
-
-
0029194459
-
The SPLASH-2 programs: Characterization and methodological considerations
-
S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, "The SPLASH-2 programs: Characterization and methodological considerations," in 22nd Int'l Symp. on Computer Architecture (ISCA), Jun. 1995, pp. 24-36.
-
22nd Int'l Symp. on Computer Architecture (ISCA), Jun. 1995
, pp. 24-36
-
-
Woo, S.C.1
Ohara, M.2
Torrie, E.3
Singh, J.P.4
Gupta, A.5
|