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Volumn , Issue , 2010, Pages 147-152
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Exploiting GPU on-chip shared memory for accelerating schedulability analysis
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Author keywords
[No Author keywords available]
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Indexed keywords
AUTOMOTIVE CONTROL UNITS;
DESIGN CYCLE;
EMBEDDED ELECTRONIC DEVICES;
GPU PROGRAMMING;
GPU-BASED ALGORITHMS;
GRAPHICS PROCESSING UNITS;
NP-HARD;
ON CHIP MEMORY;
ON CHIPS;
PARALLEL COMPUTING;
PARALLEL PROCESSING;
SCHEDULABILITY ANALYSIS;
SHARED MEMORIES;
TASK MODELS;
TIMING CONSTRAINTS;
ALGORITHMS;
AUTOMOBILE ELECTRONIC EQUIPMENT;
DESIGN;
ELECTRONICS ENGINEERING;
IMAGE CODING;
PARALLEL ARCHITECTURES;
PROGRAM PROCESSORS;
SYSTEMS ANALYSIS;
TELECOMMUNICATION EQUIPMENT;
TIMING CIRCUITS;
ELECTRONIC TIMING DEVICES;
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EID: 79952555713
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ISED.2010.36 Document Type: Conference Paper |
Times cited : (3)
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References (16)
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