Verifying thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions

Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010

Volumn , Issue , 2010, Pages 104-105

  Marchal, Paul ^a   Van Der Plas, Geert ^a   Limaye, Paresh ^a   Mercha, Abdelkarim ^a   Thijs, Steven ^a   Linten, Dimitri ^a   Guruprasad, Katti ^a   Stucchi, Michele ^a   Vandevelde, Bart ^a   Bronckers, Stephane ^a   Minas, Nikolas ^a   Cupac, Miro ^a   Dehan, Morin ^a   Nelis, Marc ^a   Agarwal, Rahul ^a   Dehaene, Wim ^a   Travaly, Youssef ^a   Beyne, Eric ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP PACKAGES; CO-DESIGN FLOW; DESIGN CHALLENGES; EXPERIMENTAL CHARACTERIZATION; MECHANICAL BEHAVIOR; NEW DESIGN; THERMOMECHANICAL SIMULATION;

THERMOMECHANICAL TREATMENT; THREE DIMENSIONAL;

DESIGN;

EID: 77957898757     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2010.5488929     Document Type: Conference Paper

References (8)

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3. H. Yoshikawa et al., "Chip-Scale Camera Module (CSCM) Using Through-Silicon-Via (TSV)," ISSCC 09, paper 28.5.
4. Y. Suntharalingam et al., "A 4-Side Tileable Back-Illuminated 3D-Integrated Mpixel CMOS Image Sensor," ISSCC 09, paper 02.1.
5. K. Ishida et al., "A 1.8V 30nJ Adaptive Program-Voltage (20V) Generator for 3D-Integrated NAND Flash SSD," ISSCC 09, paper 13.5.
6. J. Van Olmen et al., "3D stacked IC demonstration using a through Silicon Via First approach," Proc. IEDM 2008, pp. 303-306.
7. A. Jourdain et al., "Electrically yielding Collective Hybrid Bonding for 3D stacking of ICs," Proc. ECTC 2009, pp. 11-13.
8. R. Radojcic, et al, "Design for Manufacturability for Fabless Manufacturers," IEEE Solid-State Circuits Magazine, vol. 1, no. 3, pp. 25-33, summer 2009.