Fractal Coherence: Scalably verifiable cache coherence

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2010, Pages 471-482

  Zhang, Meng ^a   Lebeck, Alvin R ^b   Sorin, Daniel J ^a  

^a DUKE UNIVERSITY   (United States)

^b Duke University   (United States)

Author keywords

Cache coherence; Formal verification; Multicore

Indexed keywords

ARBITRARY NUMBER; CACHE COHERENCE; CACHE COHERENCE PROTOCOLS; COHERENCE PROTOCOL; DIRECTORY PROTOCOL; FORMAL TOOLS; FORMAL VERIFICATION; MULTICORE;

ARCHITECTURAL DESIGN; MULTIPROCESSING SYSTEMS;

FRACTALS;

EID: 79951700287     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2010.11     Document Type: Conference Paper

References (33)

1. J. A. W. Wilson. Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors. In Proc. of the 14th Annual Int'l Symposium on Computer Architecture, 1987.
2. A. R. Alameldeen and D. A. Wood. Variability in Architectural Simulations of Multi-Threaded Workloads. In Proc. of the 9th Int'l Symposium on High-Performance Computer Architecture, 2003.
3. Arvind, N. Dave and M. Katelman. Getting Formal Verification into Design Flow. In Proc. of Formal Methods, 2008.
4. L. A. Barroso et al. Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing. In Proc. of the 27th Int'l Symposium on Computer Architecture, 2000.
5. B. Bentley. Validating the IntelR PentiumR 4 Microprocessor. In Proc. of Int'l Conference on Dependable Systems and Networks, 2001.
6. D. Bergamini, N. Descoubes, C. Joubert, and R. Mateescu. Bisimulator: A Modular Tool for on-the-Fly Equivalence Checking. In Proc. of Tools and Algorithms for the Construction and Analysis of Systems, 2005.
7. S. Burckhardt, R. Alur, and M. M. K. Martin. Verifying Safety of a Token Coherence Implementation by Parametric Compositional Refinement. In Proc. of Verification, Model Checking, and Abstract Interpretation, 2005.
8. C. T. Chou, P. K. Mannava, and S. Park. A Simple Method for Parameterized Verification of Cache Coherence Protocols. In Proc. of Formal Methods in Computer-Aided Design, 2004.
9. E. M. Clarke et al. Verification of the Futurebus+ Cache Coherence Protocol. Computer Hardware Description Languages and Their Applications, vol. 32, 1993.
10. E. M. Clarke and J. M. Wing. Formal Methods: State of the Art and Future Directions. ACM Computing Surveys, vol. 28, 1996.
11. D. L. Dill, A. J. Drexler, A. J. Hu, and C. H. Yang. Protocol Verification as a Hardware Design Aid. In Proc. of IEEE Int'l Conference on Computer Design : VLSI in Computers & Processors, 1992.
12. H. Garavel, F. Lang, R. Mateescu, and W. Serwe. CADP 2006: A Toolbox for the Construction and Analysis of Distributed Processes. In Proc. of Computer Aided Verification, 2007.
13. K. Gharachorloo, M. Sharma, S. Steely, and S. V. Doren. Architecture and Design of Alphaserver GS320. In Proc. of the 9th Int'l Conference on Architectural Support for Programming Languages and Operating Systems, 2000.
14. C. N. Ip and D. L. Dill. Better Verification through Symmetry. Computer Hardware Description Languages and Their Applications, vol. 32, 1993.
15. D. Lenoski, J. Laudon, K. Gharachorloo, A. Gupta, and J. Hennessy. The Directory-Based Cache Coherence Protocol for the Dash Multiprocessor. In Proc. of the 17th annual Int'l symposium on Computer Architecture, 1990.
16. P. Loewenstein. Verification of a Multiprocessor Cache Protocol Using Simulation Relations and Higher-Order Logic. Lecture Notes in Computer Science, vol. 531, 1991.
17. P. S. Magnusson et al. Simics: A Full System Simulation Platform. Computer, vol. 35, 2002.
18. B. B. Mandelbrot. The Fractal Geometry of Nature: W.H. Freeman and Company, 1982.
19. M. M. K. Martin. Formal Verification and Its Impact on the Snooping Versus Directory Protocol Debate. In Proc. of the Int'l Conference on Computer Design, 2005.
20. M. M. K. Martin et al. Multifacet's General Execution-Driven Multiprocessor Simulator (Gems) Toolset. ACM SIGARCH Computer Architecture News, vol. 33, 2005.
21. M. R. Marty et al. Improving Multiple-Cmp Systems Using Token Coherence. In Proc. of the 11th Int'l Symposium on High-Performance Computer Architecture, 2005.
22. M. R. Marty and M. D. Hill. Virtual Hierarchies to Support Server Consolidation. In Proc. of the 34th Annual Int'l Symposium on Computer Architecture, 2007.
23. K. L. Mcmillan and C. B. Labs. Parameterized Verification of the Flash Cache Coherence Protocol by Compositional Model Checking. In CHARME 01: IFIP Working Conference on Correct Hardware Design and Verification Methods, 2001.
24. G. J. Milne. Design for Verifiability. Hardware Specification, Verification and Synthesis: Mathematical Aspects, vol. 408, 1990.
25. R. Milner. A Calculus of Communicating Systems. Journal of Computer and System Sciences, vol. 28, 1984.
26. S. Park and D. L. Dill. Verification of FLASH Cache Coherence protocol by Aggregation of Distributed Transactions. In Proc. of the 8th Annual ACM Symposium on Parallel Algorithms and Architectures, 1996.
27. F. Pong and M. Dubois. A New Approach for the Verification of Cache Coherence Protocols. IEEE Transactions on Parallel and Distributed Systems, vol. 6, 1995.
28. F. Pong, A. Nowatzyk, G. Aybay, and M. Dubois. Verifying Distributed Directory-Based Cache Coherence Protocols: S3.mp, a Case Study. In Proc. of the 1st Int'l EURO-PAR Conference, 1995.
29. S. Srinivasan, P. S. Chhabra, P. K. Jaini, A. Aziz, and L. John. Formal Verification of a Snoop-Based Cache Coherence Protocol Using Symbolic Model Checking. In Proc. of the 12th Int'l Conference on VLSI Design, 1999.
30. U. Stern and D. L. Dill. Improved Probabilistic Verification by Hash Compaction. In Proc. of Advanced Research Working Conference on Correct Hardware Design and Verification Methods, 1995.
31. S. Thoziyoor et al. Cacti 5.1. HP Technical Report, 2008.
32. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 programs: characterization and methodological considerations. In Proc. of the 22nd Annual Int'l Symposium on Computer Architecture, 1995.
33. D. A. Wood, G. A. Gibson, and R. H. Katz. Verifying a Multiprocessor Cache Controller Using Random Test Generation. IEEE Design & Test, vol. 7, 1990.