Modular fault simulation of mixed signal circuits with fault ranking by severity

Proceedings - 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1998

Volumn 1998-December, Issue , 1998, Pages 341-348

  Gomes, A V ^a   Voorakaranam, R ^a   Chatterjee, A ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; DESIGN FOR TESTABILITY; ELECTRIC SIGNAL SYSTEMS; FAULT TOLERANCE; TIMING CIRCUITS; VLSI CIRCUITS;

CIRCUIT PARTITIONING; DIAGNOSIS PROCEDURE; FAULT SIMULATION; FUNCTION APPROXIMATION; MIXED-SIGNAL CIRCUITS; NONLINEAR CIRCUIT; PARAMETER DEVIATIONS; SYSTEM-LEVEL SPECIFICATIONS;

MIXED SIGNAL INTEGRATED CIRCUITS;

EID: 79951646897     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.1998.732184     Document Type: Conference Paper

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