Statistically calculating reject limits at parametric test

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 1997, Pages 172-177

  Michelson, Diane K ^a  

^a INTERSIL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; STATISTICAL METHODS;

KNOWN GOOD DIE (KGD) METHOD;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0031357947     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)