Development and implementation of parameterized FPGA-based general purpose neural networks for online applications

IEEE Transactions on Industrial Informatics

Volumn 7, Issue 1, 2011, Pages 78-89

  Gomperts, Alexander ^a   Ukil, Abhisek ^b   Zurfluh, Franz ^b  

^a Satellite Services BV   (Netherlands)

^b ABB CORPORATE RESEARCH   (Switzerland)

Author keywords

Backpropagation; field programmable gate array (FPGA); hardware implementation; multilayer perceptron; neural network; NIR spectra calibration; spectroscopy; VHDL; Xilinx FPGA

Indexed keywords

HARDWARE IMPLEMENTATION; MULTILAYER PERCEPTRON; NIR SPECTRUM; VHDL; XILINX FPGA;

BACKPROPAGATION ALGORITHMS; CALIBRATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INFRARED DEVICES; LEARNING ALGORITHMS; LOGIC GATES; MULTILAYERS; NETWORK ARCHITECTURE; NEURAL NETWORKS; PARAMETERIZATION; SPACE PLATFORMS; SPACE RESEARCH;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 79951569015     PISSN: 15513203     EISSN: None     Source Type: Journal    
DOI: 10.1109/TII.2010.2085006     Document Type: Article

References (38)

1. I. A. Basheer and M. Hajmeer, "Artificial neural networks: Fundamentals, computing, design, and application," J. Microbio. Methods, vol. 43, pp. 3-31, Dec. 2000.
2. M. Paliwal and U. A. Kumar, "Neural networks and statistical techniques: A review of applications," Expert Systems With Applications, vol. 36, pp. 2-17, 2009.
3. B. Widrow, D. E. Rumelhart, and M. A. Lehr, "Neural networks: Applications in industry, business and science," Commun. ACM, vol. 37, no. 3, pp. 93-105, 1994.
4. A. Ukil, Intelligent Systems and Signal Processing in Power Engineering, 1st ed. New York: Springer, 2007.
5. B. Schrauwen, M. D'Haene, D. Verstraeten, and J. V. Campenhout, "Compact hardware liquid state machines on FPGA for real-time speech recognition," Neural Networks, vol. 21, no. 2-3, pp. 511-523, 2008.
6. C. Mead and M. Mahowald, "A silicon model of early visual processing," Neural Networks, vol. 1, pp. 91-97, 1988. (Pubitemid 18611446)
7. J. B. Theeten, M. Duranton, N. Mauduit, and J. A. Sirat, "The LNeuro chip: A digital VLSI with on-chip learning mechanism," in Proc. Int. Conf. Neural Networks, 1990, vol. 1, pp. 593-596.
8. J. Liu and D. Liang, "A survey of FPGA-based hardware implementation of ANNs," in Proc. Int. Conf. Neural Networks Brain, 2005, vol. 2, pp. 915-918.
9. P. Ienne, T. Cornu, and G. Kuhn, "Special-purpose digital hardware for neural networks: An architectural survey," J. VLSI Signal Process., vol. 13, no. 1, pp. 5-25, 1996.
10. A. R. Ormondi and J. Rajapakse, "Neural networks in FPGAs," in Proc. Int. Conf. Neural Inform. Process., 2002, vol. 2, pp. 954-959.
11. B. J. A. Kroese and P. van der Smagt, An Introduction to Neural Networks, 4th ed. Amsterdam, the Netherlands: The University of Amsterdam, Sep. 1991.
12. J. Zhu and P. Sutton, "FPGA implementations of neural networks-A survey of a decade of progress," Lecture Notes in Computer Science, vol. 2778/2003, pp. 1062-1066, 2003.
13. "MATLAB Neural Network Toolbox User Guide," ver. 5.1, The Math- Works Inc., Natick, MA, 2006.
14. A. Rosado-Munoz, E. Soria-Olivas, L. Gomez-Chova, and J. V. Frances, "An IP core and GUI for implementing multilayer perceptron with a fuzzy activation function on configurable logic devices," J. Universal Comput. Sci., vol. 14, no. 10, pp. 1678-1694, 2008.
15. E. Sanchez, "FPGA implementation of an adaptable-size neural network," in Proc. Int. Conf. ANN, 1996, vol. 1112, pp. 383-388. (Pubitemid 126098562)
16. A. R. Ormondi and J. Rajapakse, FPGA Implementations of Neural Networks. New York: Springer, 2006.
17. N. Izeboudjen, A. Farah, H. Bessalah, A. Bouridene, and N. Chikhi, "Towards a platform for FPGA implementation of the MLP based back propagation algorithm," Lecture Notes in Computer Science, vol. 4507/ 2007, pp. 497-505, 2007.
18. R. Gadea, R. C. Palero, J. C. Boluda, and A. S. Cortes, "FPGA implementation of a pipelined on-line backpropagation," J. VLSI Signal Process., vol. 40, pp. 189-213, 2005. (Pubitemid 40536727)
19. R. Gadea, J. Cerda, F. Ballester, and A. Mocholi, "Artificial neural network implementation on a single FPGA of a pipeline on-line backpropagation," in Proc. Int. Symp. Syst. Synthesis, 2000, pp. 225-230.
20. P. Ferreiraa, P. Ribeiroa, A. Antunes, and F. M. Dias, "A high bit resolution FPGA implementation of a FNN with a new algorithm for the activation function," Neurocomputing, vol. 71, pp. 71-77, 2007. (Pubitemid 350047388)
21. B. Girau, "Building a 2D-compatible multilayer neural network," in Proc. Int. Joint Conf. Neural Networks, 2000, pp. 59-64.
22. S. L. Bade and B. L. Hutchings, "FPGA-based stochastic neural network implementation," in Proc. IEEE Workshop FPGAs for Custom Comput. Mach., 1994, pp. 189-198.
23. J. G. Elredge and B. L. Hutchings, "RRANN A hardware implementation of the backpropagation algorithm using reconfigurable FPGAs," in Proc. IEEE World Conf. Comput. Intell., 1994, pp. 77-80.
24. G. Alizadeh, J. Frounchi, M. B. Nia, M. H. Zariff, and S. Asgarifar, "An FPGA implementation of an artificial neural network for prediction of cetane number," in Proc. Int. Conf. Comp. Comm. Eng., 2008, pp. 605-608.
25. S. Tatikonda and P. Agarwal, "Field programmable gate array (FPGA) based neural network implementation of motion control and fault diagnosis of induction motor drive," in Proc. IEEE Conf. Ind. Tech., 2008, pp. 1-6.
26. A. Mellit, H. Mekki, A. Messai, and H. Salhi, "FPGA-based implementation of an intelligent simulator for stand-alone photovoltaic system," Expert Systems With Applications, vol. 37, pp. 6036-6051, 2010.
27. A. Rahnamaei, N. Pariz, and A. Akbarimajd, "FPGA implementation of an ANN for detection of anthelmintics resistant nematodes in sheep flocks," in Proc. IEEE Conf. Ind. Electronics Applications, 2009, pp. 1899-1904.
28. "Virtex-5 FPGA User Guide," Xilinx, 2007.
29. D. E. Rumelhart, G. E. Hinton, and R. J. Williams, "Learning internal representations by error propagation," Nature, vol. 323, pp. 533-536, 1986, newblock MIT Press. (Pubitemid 16025374)
30. D. Bishop, "Fixed point package." [Online]. Available: http://www. eda.org/vhdl-200x/vhdl-200x-ft/packages/fixed-pkg.vhd
31. K. Nichols, M. Moussa, and S. Areibi, "Feasibility of floating-point arithmetic in FPGA based artificial neural networks," in Proc. Int. Conf. Computer Applications in Industry and Engineering, 2002, pp. 8-13.
32. M. Tommiska, "Efficient digital implementation of the sigmoid function for reprogrammable logic," in Proc. IEE Comput. Digital Tech., 2003, vol. 150, pp. 403-411.
33. J. Holt and J. Hwang, "Finite precision error analysis of neural network hardware implementations," IEEE Trans. Computers, vol. 42, pp. 281-290, 1993.
34. "Tecator data set" Carnegie Mellon University. [Online]. Available: http://lib.stat.cmu.edu/datasets/tecator
35. A. Ukil, J. Bernasconi, H. Braendle, H. Buijs, and S. Bonenfant, "Improved calibration of near-infrared spectra by using ensembles of neural network models," IEEE Sensors J., vol. 10, no. 3, pp. 578-584, Mar. 2010.
36. M. Holler, S. Tam, H. Castro, and R. Benson, An Electrically Trainable Artificial Neural Network (ETANN) With 10240 "Floating Gate" Synapses. Piscataway, NJ: IEEE Press, 1990, pp. 50-55.
37. D. Hammerstrom, "A VLSI architecture for high-performance, lowcost, on-chip learning," in Proc. Int. Joint Conf. NN, 1990, vol. 2, pp. 537-544.
38. E. van Keulen, S. Colak, H. Withagen, and H. Hegt, "Neural network hardware performance criteria," in Proc. IEEE World Congr. Comput. Intell., 1994, vol. 3, pp. 1955-1958.