Application of generalized linear models to predict semiconductor yield using defect metrology data

IEEE Transactions on Semiconductor Manufacturing

Volumn 24, Issue 1, 2011, Pages 44-58

  Krueger, Dana C ^a   Montgomery, Douglas C ^b   Mastrangelo, Christina M ^c  

^a KANSAS STATE UNIVERSITY   (United States)

^b Arizona State University   (United States)

^c UNIVERSITY OF WASHINGTON   (United States)

Author keywords

Defect modeling; generalized linear models; logistic regression; semiconductor yield; yield modeling

Indexed keywords

DEFECT MODELING; GENERALIZED LINEAR MODELS; LOGISTIC REGRESSION; SEMICONDUCTOR YIELD; YIELD MODELING;

FORECASTING; MATHEMATICAL MODELS; REGRESSION ANALYSIS;

DEFECTS;

EID: 79951564685     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2010.2089377     Document Type: Article

References (15)

1. S. P. Cunningham, C. J. Spanos, and K. Voros, "Semiconductor yield improvement: Results and best practices," IEEE Trans. Semiconduct. Manuf., vol. 8, no. 2, pp. 103-109, May 1995.
2. C. H. Stapper, "Fact and fictions in yield modeling (ICs)," Microelectron. J., vol. 20, nos. 1-2, pp. 129-151, 1989.
3. N. Kumar, K. Kennedy, K. Gildersleeve, R. Abelson, C. M. Mastrangelo, and D. C. Montgomery, "A review of yield modeling techniques for semiconductor manufacturing," Int. J. Prod. Res., vol. 44, no. 23, pp. 5019-5036, 2006. (Pubitemid 44627508)
4. C. Yeh, C. Chen, and K. Chen, "Validation and evaluation for defectkill- rate and yield estimation models in semiconductor manufacturing," Int. J. Prod. Res., vol. 45, no. 4, pp. 829-844, 2007.
5. A. Lorenzo, D. Oter, S. Cruceta, J. F. Valtuena, G. Gonzalez, and C. Mata, "Kill ratio calculation for in line yield prediction," Proc. SPIE: Int. Soc. Optic. Eng., vol. 3743, no. 258, pp. 258-266, 1999.
6. C. N. Berglund, "Unified yield model incorporating both defect and parametric effects," IEEE Trans. Semiconduct. Manuf., vol. 9, no. 3, pp. 447-454, Aug. 1996. (Pubitemid 126776274)
7. N. Kumar, "Hierarchical modeling approach to improve factory operations in semiconductor manufacturing," Ph.D. Dissertation, Dept. Industr. Eng., Univ. Washington, Seattle, 2006.
8. C. H. Wang, "Recognition of semiconductor defect patterns using spatial filtering and spectral clustering," Expert Syst. Applicat., vol. 34, no. 3, pp. 1914-1923, Apr. 2008.
9. H. H. Fellows, C. M. Mastrangelo, and K. P. White, Jr., "An empirical comparison of spatial randomness models for yield analysis," IEEE Trans. Electron. Packag. Manuf., vol. 32, no. 2, pp. 115-120, Apr. 2009.
10. K. R. Skinner, D. C. Montgomery, G. C. Runger, J. W. Fowler, D. R. McCarville, T. R. Rhoads, and J. D. Stanley, "Multivariate statistical methods for modeling and analysis of wafer probe test data," IEEE Trans. Semiconduct. Manuf., vol. 15, no. 4, pp. 523-530, Nov. 2002.
11. H. Hu, "Supervised learning models in sort yield modeling," in Proc. Adv. Semiconduct. Manuf. Conf., 2009, pp. 133-136.
12. D. C. Montgomery, E. A. Peck, and G. G. Vining, Introduction to Linear Regression Analysis, 4th ed. Hoboken, NJ: Wiley, 2006, ch. 14.
13. J. A. Nelder and R. W. M. Wedderburn, "Generalized linear models," J. Royal Statistic. Soc., Series A (General), vol. 135, no. 3, pp. 370-384, 1972.
14. T. Hu and S. Y. Sung, "A trimmed mean approach to finding spatial outliers," Intelligent Data Anal., vol. 8, no. 1, pp. 79-95, 2004.
15. J. A. Cunningham, "The use and evaluation of yield models in integrated circuit manufacturing," IEEE Trans. Semiconduct. Manuf., vol. 3, no. 2, pp. 60-71, May 1990.