Pipelined FPGA adders

Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010

Volumn , Issue , 2010, Pages 422-427

  De Dinechin, Florent ^a   Nguyen, Hong Diep ^a   Pasca, Bogdan ^a  

^a UNIVERSITÉ DE LYON   (France)

Author keywords

Addition; FPGA; Low latency; Pipeline

Indexed keywords

ADDER ARCHITECTURE; ADDITION; BIT-WIDTH; BUILDING BLOCKES; CARRY SELECT ADDERS; ELLIPTIC CURVE CRYPTOGRAPHY; FPGA; LOW-LATENCY; OPERATING FREQUENCY; RESOURCE ESTIMATION; RIPPLE CARRY ADDERS;

ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FREQUENCY ESTIMATION;

ADDERS;

EID: 79551558541     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2010.87     Document Type: Conference Paper

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