Pipelined adders

IEEE Transactions on Computers

Volumn 45, Issue 3, 1996, Pages 348-356

  Dadda, Luigi ^a,b   Piuri, Vincenzo ^a,b  

^a POLITECNICO DI MILANO   (Italy)

^b IEEE

Author keywords

Adders; High speed adders; High throughput adders; Pipelined computation; Skewed arithmetic

Indexed keywords

EID: 0000588107     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.485573     Document Type: Article

References (9)

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2. J.M. Muller, Arithmetique des Ordinateurs. Paris: Masson, 1989.
3. G. Corbaz, J. Duprat, B. Hocher, and J.M. Muller, "Implementation of a VLSI Polynomial Evaluator for Real-Time Applications," Proc. Int'l Conf. Application-Specific Array Processors (ASAP'91), pp. 13-24, Barcelona, Aug. 1991.
4. G. Goggi, B. Lofstedt, et al., "A Digital Front-End and Read-Out Microsystem for Calorimetry at LHC - Digital Filters," Report on the FERMI Project of the European Organization for Nuclear Research, CERN/DRDC/92-26 RD-16, pp. 36-41, May 1, 1992.
5. D. Somasekhar and V. Visvanathan, "A 230 MHz Half Bit-Level Pipelined Multiplier Using True Single-Phase Clocking," Proc. Sixth Int'l Conf. VLSI Design, pp. 347-350, Bombay, Dec. 1993.
6. S.P. Johansen, "Systolic Evaluation of Functions: Digit-Level Algorithm and Realization," Proc. Int'l Conf. Application-Specific Array Processors (ASAP'93), pp. 514-523, Venice, Oct. 1993.
7. I. Koren, Computer Arithmetic Algorithms. Englewood Cliffs, N.J.: Prentice-Hall, 1993.
8. M. Mehta, V. Parmar, and E.E. Swartzlander, "High-Speed Multiplier Design Using Multi-Input Counters and Compressor Circuits," Proc. Int'l Symp. Computer Arithmetic, pp. 43-50, 1991.
9. S. Kawahito, M. Ishida, T. Nakamura, M. Kamayama, and T. Higuchi, "High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits," IEEE Trans. Computers, vol. 43, no. 1, pp. 34-42, Jan. 1994.