FPGA adders: Performance evaluation and optimal design

IEEE Design and Test of Computers

Volumn 15, Issue 1, 1998, Pages 24-29

  Xing, Shanzhen ^a   Yu, William W H ^a,b,c  

^a UNIVERSITY OF HONG KONG   (Hong Kong)

^b CHUNG YUAN CHRISTIAN UNIVERSITY   (Taiwan)

^c IEEE   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COSTS; DIGITAL ARITHMETIC; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; OPTIMIZATION;

ARITHMETIC LOGIC UNIT (ALU); FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

ADDERS;

EID: 0031677758     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.655179     Document Type: Review

References (10)

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10. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, A Systems Perspective, Addison-Wesley, Reading, Mass., 1985.