An interior point optimization solver for real time inter-frame collision detection: Exploring resource-accuracy-platform tradeoffs

Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010

Volumn , Issue , 2010, Pages 113-118

  Leung, Brian ^a   Wu, Chih Hung ^a   Memik, Seda Ogrenci ^a   Mehrotra, Sanjay ^a  

^a Northwestern University   (United States)

Author keywords

Collision detection; CUDA; FPGA; GPGPU; Linear Programming

Indexed keywords

COLLISION DETECTION; CUDA; FIXED POINTS; FLOATING POINT IMPLEMENTATION; FLOATING POINTS; FPGA; FPGA IMPLEMENTATIONS; GPGPU; INTER-FRAME; INTERIOR POINT; INTERIOR POINT ALGORITHM; OBJECT RESOLUTION; OPTIMIZATION SOLVERS; POLYHEDRAL OBJECTS; PRECISION FLOATING POINT; REAL TIME; RESOURCE USAGE; SYSTEM EFFICIENCY;

ALGORITHMS; DIGITAL ARITHMETIC; LINEAR PROGRAMMING; OPTIMIZATION; PROGRAM PROCESSORS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 79551513358     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2010.31     Document Type: Conference Paper

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