A host/co-processor FPGA-based architecture for fast image processing

2007 4th IEEE Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, IDAACS

Volumn , Issue , 2007, Pages 373-378

  Kalomiros, John A ^a   Lygouras, John ^b  

^a TECHNOLOGICAL EDUCATIONAL INSTITUTE OF SERRES   (Greece)

^b DEMOCRITUS UNIVERSITY OF THRACE   (Greece)

Author keywords

Embedded processors; FPGAs; Hardware design; Image processing

Indexed keywords

CELLULAR RADIO SYSTEMS; CIVIL AVIATION; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER ARCHITECTURE; DATA ACQUISITION; DATA STORAGE EQUIPMENT; DIGITAL IMAGE STORAGE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE PROCESSING; IMAGING SYSTEMS; IMAGING TECHNIQUES; INTELLIGENT SYSTEMS; MERGERS AND ACQUISITIONS; MICROPROCESSOR CHIPS; MOTION ESTIMATION; OPTICAL DATA PROCESSING; STANDARDS; TECHNOLOGY; TECHNOLOGY TRANSFER; VIDEO RECORDING; WAVE FILTERS;

ALTERA CYCLONE; CO PROCESSORS; COMMUNICATION CHANNELS; COMPUTING SYSTEMS; EMBEDDED PROCESSORS; EXTERNAL-; FIELD PROGRAMMABLE GATE ARRAY; FPGA BOARDS; FPGAS; FRAME GRABBER; HARDWARE DESIGN; HARDWARE FILTERING; HIGH SPEEDS; HOST COMPUTERS; INTELLIGENT DATA; LAB VIEW; MACRO CELLS; ON-CHIP MEMORIES; PROCESSING TIMES; SOFTWARE PROCESSOR; SYSTEM ARCHITECTURES; SYSTEM PERFORMANCES; SYSTEM-ON-A-PROGRAMMABLE-CHIP; TRANSFER RATES; VIDEO DATA;

COMPUTER SYSTEMS;

EID: 50149101176     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IDAACS.2007.4488442     Document Type: Conference Paper

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