Design of an energy-efficient 32-bit adder operating at subthreshold voltages in 45-nm CMOS

ICCE 2010 - 3rd International Conference on Communications and Electronics

Volumn , Issue , 2010, Pages 87-91

  Tran, Anh T ^a   Baas, Bevan M ^a  

^a University of California Davis   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BATTERY CAPACITY; CHIP PACKAGING; COMPUTATIONAL PLATFORMS; ENERGY EFFICIENT; FUNCTIONAL UNITS; HIGH COSTS; LOW ENERGY CONSUMPTION; LOW POWER; LOW-POWER CIRCUIT; MAXIMUM OPERATING FREQUENCY; PORTABLE DEVICE; SIMULATION RESULT; SUBTHRESHOLD;

COMPUTATIONAL EFFICIENCY; COOLING SYSTEMS; DESIGN; ENERGY UTILIZATION; MICROPROCESSOR CHIPS;

ENERGY EFFICIENCY;

EID: 78751497257     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCE.2010.5670687     Document Type: Conference Paper

References (10)

1. A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, "Low power CMOS digital design," JSSC, vol. 27, pp. 473-484, 1992.
2. A. Wang and A. P. Chandrakasan, "A 180-mv subthreshold fft processor using a minimum energy design methodology," IEEE JSSC, vol. 40, no. 1, pp. 310-319, 2005.
3. PTM, "Predictable technology model," Online, http://ptm.asu.edu/.
4. W. Zhao and Y. Cao, "New generation of predictive technology model for sub-45nm early design exploration," IEEE TED, vol. 53, pp. 2816-2823, Nov. 2006.
5. I. Koren, Computer Arithmetic Algorithms, A K Peters Ltd., second edition, 2002.
6. J. M. Rabaey, A. Chandrakasan, and B. Nikolić, Digital Integrated Circuits: A Design Perspective, Prentice-Hall, New Jersey, U.S.A, second edition, 2003.
7. R. Ho, K. W. Mai, and M. A. Horowitz, "The future of wires," Proceedings of the IEEE, vol. 89, pp. 490-504, Apr. 2001.
8. P. K. Chan, M. D. F. Schlag, et al., "Delay optimization of carry-skip adders and block carry-look ahead adders using multidimentional dynamic programming," IEEE Trans. on Computers, vol. 41, no. 8, pp. 920-930, 1992.
9. V. Kantabutra, "Designing optimum one-level carry-skip adders," IEEE Trans. on Computers, vol. 42, no. 6, pp. 759-764, 1993.
10. A. Wang, B. H. Calhoun, and A. P. Chandrakasan, Sub-threshold Design for Ultra Low-Power Systems, Springer Science, first edition, 2006.